A HIGH SPEED DISTRIBUTED FIFO SCHEME FOR MANAGING INTERCONNECTS
Abstract:- Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as well as the transistors. Scaling trends allow for complete systems to be built on a single chip (SoC), but they require long interconnects for global signals and clock distribution networks. The parasitic of these global interconnects make efficient and high-performance operation difficult. On-chip communication shortly will require tens of clock cycles for signal propagation between communicating modules/components. This communication is becoming less reliable as feature size and power supply voltages decrease, thus increasing the effect of environmental and process variations. Currently, repeater insertion is widely used to improve global interconnect delays, but with very high latency. In this thesis, an asynchronous distributed rst-in, rst-out (FIFO) buffer is proposed to facilitate communication between modules of highly integrated SoCs. A synchronous FIFO is built for comparison. Using an asynchronous FIFO helps alleviate the clock skew, clock distribution and single clock synchronization problems associated with high-speed, synchronous digital design. The distributed FIFO buffer scheme also improves latency considerably. In addition, this asynchronous FIFO scheme has very good tolerance to voltage and temperature variations. The buffer control circuitry is self-timed and allows for ease of interfacing in multiple domain clock designs. The asynchronous FIFO allows a maximum data transfer rate of 1.67 GHz and 2.35 GHz in a 0:25_m and 0:18_m technology respectively.