Adaptive beamforming plays an important role in sensor array systems in countering interference outside of the direction of interest. However, calculation of the adaptive weights generally requires a large number of operations that rapidly grows with the number of antennas. Consequently, a large number of programmable processors is commonly required to calculate the weights, which in some systems may present excessive weight, volume and power requirements.Field programmable gate arrays (FPGAs) offer a credible alternative to re-programmable technology for implementing digital signal processing. Current devices provide the equivalent of 6 million programmable gates, and dedicated fixed-point multipliers. These support performances in the range of 50 GOPS for the fixed-point filtering and beamforming functions required by radar and communications systems. Furthermore, devices are emerging that contain embedded processors and high-speed serial interfaces. This functionality allows interfaces to be constructed that simplify integration of FPGAs with RISC processors for handling of back-end processing and control.