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Automated Generation of Cycle Level Simulators for Embedded Processors
Post: #1

Embedded processors are changing the world. The development of scenario specific
processors with an emphasis on a highly specific functionality, fast development time and
high reliability has opened up several new vistas for the future of microprocessor
development. With the development of embedded processors likely to become THE
happening field in the next few years, an absolute necessity in processor development is
the use of a processor simulation tool to validate new embedded processor designs and
obtain performance statistics. Tools that automatically generate these simulators have
tremendous applicability. This project is an attempt at developing one such Automated
Generator of Cycle Level Simulators for Embedded Microprocessors.
The generator should conform to a number of requirements. It should be easy to use, after
all, the purpose of an automated generator is to prevent the user from making his very
own hand coded simulator by providing at least reasonable time gains. It should permit
the user to enter all kinds of processor details in a simple, yet highly flexible and powerful
manner. It should provide him with a number of modules that simulate commonly
prevalent processor functionality to simplify the entry procedure and generate new
modules of his own, if necessary. Once the processor details are assimilated and the
simulator generated, functionality must be provided to validate the execution of some
input programs as well as the collection of performance statistics. Several options must be
provided as well permitting the user to customize the manner of execution, for example,
the extent of coupling of performance and functionality. But most importantly, the
simulator generated should be on par with the hand coded equivalents as far as execution
time of sample input programs is concerned.

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