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BiCMOS Technology
Post: #1

The need for high-performance, low-power, and low-cost systems for network transport and wireless communications is driving silicon technology toward higher speed, higher integration, and more functionality.

Further more, this integration of RF and analog mixed-signal circuits into high-performance digital signal-processing (DSP) systems must be done with minimum cost overhead to be commercially viable.

While some analog and RF designs have been attempted in mainstream digital-only complimentary metal-oxide semiconductor (CMOS) technologies, almost all designs that require stringent RF performance use bipolar or semiconductor technology.

Silicon integrated circuit (IC) products that, at present, require modern bipolar or BiCMOS silicon technology in wired application space include the essential optical network (SONET) and synchronous digital hierarchy (SDH) operating at 10 Gb/s and higher.
The viability of a mixed digital/analog. RF chip depends on the cost of making the silicon with the required elements; in practice, it must approximate the cost of the CMOS wafer, Cycle times for processing the wafer should not significantly exceed cycle times for a digital CMOS wafer.

Yields of the SOC chip must be similar to those of a multi-chip implementation. Much of this article will examine process techniques that achieve the objectives of low cost, rapid cycle time, and solid yield...
Post: #2
BiCMOS Technology
Combines Bipolar and CMOS transistors in a single integrated circuit
By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually.
Characteristics of CMOS Technology
Lower static power dissipation
Higher noise margins
Higher packing density – lower manufacturing cost per device
High yield with large integrated complex functions
High input impedance (low drive current)
Scaleable threshold voltage
High delay sensitivity to load (fan-out limitations)
Low output drive current (issue when driving large capacitive loads)
Low transconductance, where transconductance, gm a Vin
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device
Characteristics of Bipolar Technology
Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency characteristics
Better analogue capability
Improved I/O speed (particularly significant with the growing importance of package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current)
low voltage swing logic
low packing density
low delay sensitivity to load
high gm (gm a Vin)
high unity gain band width (ft) at low currents
essentially unidirectional
Combine advantages in BiCMOS Technology
• It follows that BiCMOS technology goes some way towards combining the virtues
of both CMOS and Bipolar technologies
• Design uses CMOS gates along with bipolar totem-pole stage where driving of high
capacitance loads is required
• Resulting benefits of BiCMOS technology over solely CMOS or solely bipolar :
• Improved speed over purely-CMOS technology
• Lower power dissipation than purely-bipolar technology (simplifying packaging and board requirements)
• Flexible I/Os (i.e., TTL, CMOS or ECL) –
BiCMOS technology is well suited for I/O intensive applications.
ECL, TTL and CMOS input and output levels can easily be generated with no
speed or tracking consequences
• high performance analogue
• Latchup immunity (Discussed later in course)
The simplified BiCMOS Inverter
• T3 & T4 present low impedances when turned on into saturation & load CL will be
charged or discharged rapidly
• Output logic levels will be good & will be close to rail voltages since VCEsat is quite
small & VBE » 0.7V. Therefore, inverter has high noise margins
• Inverter has high input impedance, i.e., MOS gate input
• Inverter has low output impedance
• Inverter has high drive capability but occupies a relatively small area
• However, this is not a good arrangement to implement since no discharge path
exists for current from the base of either bipolar transistor when it is being turned
off, i.e.,
• when Vin=Vdd, T2 is off and no
conducting path to the base of T4 exists
• when Vin=0, T1 is off and
no conducting path to the base of T3 exists
This will slow down the action of the circuit

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