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Direct Memory Access
Post: #1

The Idea Of Direct Memory Access
By providing circuitry to generate addresses and memory control signals independently of the processor we see that it is possible to improve performance considerably. All that is necessary is to provide a signal to tell the processor to remove itself from the bus so there is no contention on the memory control, address, or data lines.

This is the entire concept behind direct memory access (DMA). To complete our picture, it is important to note that there are actually several ways that DMA can be done. In particular, there are three common choices:-

burst mode DMA :- In burst mode the DMA controller transfers an entire block of data without interruption. During the time of the transfer, the DMA controller retains complete control of the processor's bus.

Cycle Stealing :- If it is desirable to let the processor do some processing while the DMA controller transfers data cycle stealing can be used. In this case, the DMA controller will periodically request use of the bus until all of its data are transferred. This slows down the processor and the DMA transfer.

Transparent DMA :- It is possible for the DMA controller to monitor the internal status of the processor. In those cases where the processor does not need bus access (internal data moves and such) the DMA controller uses the bus. This slows down the DMA transfer, but not the processor.

The proper transfer mode to use is determined by the system requirements.

Burst Mode DMA
Burst mode DMA is a typical way of handling bulk data transfers (like the idea we described for our video controller). The other modes operates in a similar fashion. For a burst mode transfer:-

1) The processor loads the DMA controller with the start address of the destination in memory and the number of words to transfer.

2) When the device delivering or requesting data is ready, the DMA controller is signaled. In turn, the
controller signals the processor that a DMA transfer is pending.

3) The processor acknowledges the request, finishes its current instruction, and then floats the address, control, and data buses.

4) The DMA controller now provides address and control signals to memory while the device requesting the transfer supplies or receives the data.

5) Once the transfer is complete, the DMA signals the processsor to resume its normal operation.

The signaling of the 8088 processor is done through the hold and holda lines. When the DMA controller wants the bus, it signals the processor by raising hold. After the processor completes the current
instruction, it tri-states the data, address, and control lines, and raises hold acknowledge (holda). Once the DMA controller sees holda, it knows it is free to use the bus.
Post: #2
Direct Memory Access


What is DMA

Direct memory access (DMA) is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards and sound cards. DMA is used for transferring data between the local memory and the main memory. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time and allowing computation and data transfer concurrency


DMA is an essential feature of all modern computers, as it allows devices to transfer data without subjecting the CPU to a heavy overhead. Otherwise, the CPU would have to copy each piece of data from the source to the destination, making itself unavailable for other tasks. This situation is aggravated because access to I/O devices over a peripheral bus is generally slower than normal system RAM. With DMA, the CPU gets freed from this overhead and can do useful tasks during data transfer (though the CPU bus would be partly blocked by DMA). In the same way, a DMA engine in an embedded processor allows its processing element to issue a data transfer and carries on its own task while the data transfer is being performed.

DMA Operation

There are three independent channels for DMA transfers. Each channel receives its trigger for the transfer through a large multiplexer that chooses from among a large number of signals. When these signals activate, the transfer occurs.
The DMA controller receives the trigger signal but will ignore it under certain conditions. This is necessary to reserve the memory bus for reprogramming and non-maskable interrupts etc. The controller also handles conflicts for simultaneous triggers. The priorities can be adjusted using the DMA Control Register 1 (DMACTL1). When multiple triggers happen simultaneously, they occur in order of module priority. The DMA trigger is then passed to the module whose trigger activated. The DMA channel will copy the data from the starting memory location or block to the destination memory location or block. There are many variations on this, and they are controlled by the DMA Channel Control Register
Post: #3
paper presentation of direct memory access

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