Even though the word DRAM has been quite common among us for many decades, the development in the field of DRAM was very slow. The storage medium reached the present state of semiconductor after a long scientific research. Once the semiconductor storage medium was well accepted by all, plans were put forward to integrate the logic circuits associated with the DRAM along with the DRAM itself. However, technological complexities and economic justification for such a complex integrated circuit are difficult hurdles to overcome. Although scientific breakthroughs are numerous in the commodity DRAM industry, similar techniques are not always appropriate when high- performance logic circuits are included on the same substrate. Hence, eDRAM pioneers have begun to develop numerous integration schemes. Two basic integration philosophies for an eDRAM technology are:
Â¢ Incorporating memory circuits in a technology optimized for low-Cost high performance logic.
Â¢ Incorporating logic circuits in a technology optimized for high- Density low performance DRAM.
This seemingly subtle semantic difference significantly impacts mask count, system performance, peripheral circuit complexity, and total memory capacity of eDRAM products. Furthermore, corporations With aggressive commodity DRAM technology do not have expertise in the design of complicated digital functions and are not able to assemble a design team to complete the task of a truly merged DRAM-logic product. Conversely, small application specific integrated circuit (ASIC) design corporations, unfamiliar with DRAM- specific elements and design practice, cannot carry out an efficient merged logic design and therefore mar the beauty of the original intent to integrate. Clearly, the reuse of process technology is an enabling lhetor en route to cost-effective eDRAM technology. By the same. account, modern circuit designers should be familiar with the new elements of eDRAM technology so that they can efficiently reuse DRAM-specific structures and elements in other digital functions. The reuse of additional electrical elements is a methodology that will make eDRAM more than just a memoryâ„¢ interconnected to a few million Boolean gates.
In the following sections of this report the DRAM applications and architectures that are expected to form the basis of eDRAM products are reviewed. Then a description of elements found in generic eDRAM technologies is presented so that non-memory-designers can become familiar with eDRAM specific elements and technology. Various technologies used in eDRAM are discussed. An example of eDRAM is also discussed towards the end of the report.
It can be clearly seen from this report that embedded DRAM macro extends the on-chip capacity to more than 40 MB, allowing historically off-chip memory to be integrated on chip and enabling System-on-a-Chip (SoC) designs. ËœBy these memory integrated, on chips, the bandwidth is increased to a high , extend. A highly integrated DRAM approach also simplifies board design, hereby reducing overall system cost and time to market. Even, more importantly, embedding DRAM enables higher bandwidth by allowing a wider on-Chip buss and saves power by eliminating DRAM I/O.
WHY embedded DRAM?
As application-specific integrated circuit (ASIC) technologies expand into new markets, the need for denser embedded memory grows. To accommodate this increase demand, embedded DRAM macros have been offered in state-of-the-art ASIC library portfolios. It can be made clear from this report that embedded DRAM macro extends the on-chip capacity largely, allowing historically off-chip memory to be integrated on chip and enabling System-on-a-Chip (SoC) designs. With memory on the chip, applications can take advantage of the high bandwidth naturally offered by a wide-I/O DRAM and achieve data rates greater than those previously limited by pin count and off-chip pin rates. Applications for this memory include network processors, digital signal processors, and cache chips for microprocessors. The integration of embedded DRAM into ASIC designs intensified the focus on how best to architect, design, and test a high-performance, high density macro as complex as dynamic RAM in an ASIC logic environment. The ASIC environment itself presents many difficult elements that have historically challenged DRAMsâ€specifically
wide voltage axial temperature operating ranges and uncertainties in surrounding noise conditions. These challenges dictate a robust architecture that is noise-tolerant and can operate at high voltage for performance and at low voltage for- reduced power. With the advent of embedded DRAM offerings in a logic-based ASIC technology, the performance of embedded DRAM macros has improved significantly over that of DRAM-based technologies
Fundamental DRAM operation
Embedded DRAM working can be explained effectively starting with DRAM working. DRAM memory arrays are composed of wordlines (or rows) and bitlines (columns); At the crosspoint of every row and column is a storage cell consisting of a transistor and capacitor. The data state of the cell is stored as charge on the capacitor, with the transistor acting as a switch controlling access to the capacitor. With the switch on (wordline activated), charge can be read from or written to the storage cell. The rest of the DRAM support circuits
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