The introduction of FinFET Technology has opened new chapters in Nano-technology. Simulations show that FinFET structure should be scalable down to 10 nm. Formation of ultra thin fin enables suppressed short channel effects.
It is an attractive successor to the single gate MOSFET by virtue of its superior electrostatic properties and comparative ease of manufacturability.
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits.
The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body.
The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult.
The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
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Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub- 45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (gm/gDS) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies.
To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks.
2.1 FinFET structure and layout
• The double-gate FinFET—a promising candidate to continue CMOS scaling deep into the nanometer regime
• Gate straddles thin silicon fin, forming two conducting channels on sidewalls
3.1 3D view of FinFET
2.2 Layout similar to bulk-Si MOSFET
Fig. 2.2 Bulk-Si MOSFET
Fig. 2.3 Multi-fin layout
Source (all images): T-J King, et al, “FinFET Technology Optimization…”
2.3 FinFET modeling approach
• Need a suitable SPICE model for initial design based on transistor I-V and high-frequency AC characteristics
• Modeling approaches
• Small-signal equivalent model
• Uses simple lumped circuit elements
• Suitable for only selected bias points
• Avoids need for complete device model
• Valid only for small-signal operation
• Subcircuit model (adapt 60-GHz CMOS approach)
• Begin with core BSIMSOI model
• Extend core subcircuit with extrinsic parasitics (BSIMSOI3.1 already includes gate resistance model)
• DC I-V curve fitting to extract core BSIM parameters
• Small-signal Y-parameter fitting to extract parasitic component values
• Also suitable for large-signal simulation
Give Research paper about finfet technology
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