**Post: #1**

sir thank you for your reply on radix-4 booth multiplier.it help me alot but sir i am not able to run its VHDL program.it show me an error.our teachers r also not able to rectify that error.so i have only one solution and that is you.please sir help me either send me the rectified program or kindly suggest me some other websit by which i am able to complete my project on radix-4 booth multiplier.

the program is as follow : (if needed)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

use ieee.numeric_std.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity booth_encoder is

-- generic(N : integer:=8);

Port ( a : in std_logic_vector(7 downto 0);

arg : in std_logic_vector(2 downto 0);

pprod : out std_logic_vector(15 downto 0));

end booth_encoder;

architecture Behavioral of booth_encoder is

function encoder(arg1: std_logic_vector(2 downto 0);data:std_logic_vector(7

downto 0))

return std_logic_vector is

variable temp,temp1,temp2: std_logic_vector(8 downto 0);

variable sign: std_logic;

begin

case arg1 is

when "001"|"010" =>

if data <0 then

temp:='1'& data;

else

temp:='0'&data;

end if;

when "011" =>

if data<0 then

temp1:='1'&data;

temp:=temp1(7 downto 0)&'0';

else

temp:='0'&data(6 downto 0)&'0';

end if ;

when "100" =>

if data<0 then

temp1:='1'&data;

temp2:=(not temp1)+"000000001";

temp:=(temp2(7 downto 0)&'0');

else

temp1:='0'&data;

temp2:=(not temp1)+"000000001";

temp:=(temp2(7 downto 0)&'0');

end if;

when "101"|"110" =>

if data < 0 then

temp1:='1'&data;

temp:=not(temp1)+"000000001";

else

temp1:='0'&data;

temp:=(not temp1)+"000000001";

end if;

when others =>

temp:="000000000";

--"(others=>'0');

end case;

return temp;

end encoder;

signal s1: std_logic_vector(8 downto 0);

signal s2: std_logic;

begin

s1<=encoder(arg,a);

--s2<=s1(8);

--pprod<=s2&s2&s2&s2&s2&s2&s2&s2&s1(7 downto 0);

pprod<=sxt(s1,16);

end Behavioral;

sir i am waiting for your reply.