This project provides the experience of applying an advanced version of Spurious Power Suppression Technique (SPST) on multipliers for high speed and low power purposes. When a portion of data does not affect the final computing results, the data controlling circuits of SPST latch this portion to avoid useless data transition occurring inside the arithmetic units, so that the useless spurious signals of arithmetic units are filter out. Modified Booth Algorithm is used in this project for multiplication which reduces the number of partial product to n/2.
To filter out the useless switching power, there are two approaches, i.e using registers and using AND gates, to assert the data signals of multipliers after data transition. The simulation result shows that the SPST implementation with AND gates owns an extremely high flexibility on adjusting the data asserting time which not only facilitates the robustness of SPST but also leads to a significant speed improvement and power reduction
SPURIOUS POWER SUPPRESSION TECHNIQUE
The SPST uses a detection logic circuit to detect the effective data range of arithmetic units, e.g. adders, or multipliers.
The proposed technique adopts the design concept of separating the arithmetic units into Most Significant Part (MSP) and Least Significant Part (LSP), and then freezing the MSP whenever this part of circuits does no affect the computation result.
There is a data asserting control realized by using registers or AND to further filter out the useless spurious signals of the arithmetic units every time when the latched portion is turned on.