The Itanium brand extends Intel's reach into the highest level of computing enabling powerful servers and high- performance workstations to address the increasing demands that the internet economy places on e-business. The Itanium architecture is a unique combination of innovative features, such as explicit parallelism, predication, speculation and much more. In addition to providing much more memory that today's 32-bit designs, the 64-bit architecture changes the way the processor hardware interacts with code. The Itanium is geared toward increasingly power-hungry applications like e-commerce security, computer-aided design and scientific modeling.
Intel said the Itanium provides a 12-fold performance improvement over today's 32-bit designs. Its "Explicitly Parallel Instruction Computing"(EPIC) technology enables it to handle parallel processing differently than previous architectures, most of which were designed 10 to 20 years ago. The technology reduces hardware complexity to better enable processor speed upgrades. Itanium processors contain "massive chip execution resources", that allow "breakthrough capabilities in processing terabytes of data". Itanium is the first processor to use EPIC(Explicit Parallel Instruction Computing) architecture.Its performance is to be better than the present day Reduced Instruction Set Computing and Complex Instruction Set Computing(RISC & CISC).
In modern Processors,including Itanium,a multiplicity of arithmetic-logic or floating-point on-chip units execute several instructions in parallel.Ideally,increasing the number of execution units should increas the number of extra instructions per clock cycle proportionally.But conventional processors also needs a lot of extra on-chip circuitry to schedule and track the instruction progress,which takes up valuable space,consumes power and add steps to the execution process.As a result only a slight improvement in the number of instructions per clock cycle occurs when the number of execution units are increased.Instead EPIC architects use a compiler to schedule instructions.