The Itanium brand extends Intelâ„¢s reach into the highest level of computing enabling powerful servers and high- performance workstations to address the increasing demands that the internet economy places on e-business. The Itanium architecture is a unique combination of innovative features, such as explicit parallelism, predication, speculation and much more.
In addition to providing much more memory that todayâ„¢s 32-bit designs, the 64-bit architecture changes the way the processor hardware interacts with code. The Itanium is geared toward increasingly power-hungry applications like e-commerce security, computer-aided design and scientific modeling.
Intel said the Itanium provides a 12-fold performance improvement over todayâ„¢s 32-bit designs. Its Explicitly Parallel Instruction Computing(EPIC) technology enables it to handle parallel processing differently than previous architectures, most of which were designed 10 to 20 years ago. The technology reduces hardware complexity to better enable processor speed upgrades. Itanium processors contain massive chip execution resources, that allow breakthrough capabilities in processing terabytes of data.
Here a sincere attempt is made to explore the architecture feature and performance characteristic of Itanium processor. A brief explanation on the system environment and their computing applications is also undertaken.
Â¢ TODAYâ„¢S ARCHITECTURE CHALLENGES
Â¢ IA-64 ARCHITECTURE PERFORMANCE FEATURES
Â¢ IA-64 SYSTEM ENVIRONMENT
Â¢ RAS FEATURES
Â¢ BENEFITS OF ITANIUM PROCESSORS FOR DIFFERENT PLATFORMS
Â¢ INTEL ITANIUM 2 PROCESSOR
Â¢ FUTURE SCOPE
The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980â„¢s or the 1990â„¢s.Yet,customers continued demand greater application performance.
The Itanium processor family was developed as a response to address the future performance and growth needs of business, technical and scientific users with greater flexibility, better performance and a much greater Ëœbang for the buckâ„¢ in the price performance arena. Itanium is the first processor to use EPIC(Explicit Parallel Instruction Computing) architecture. Its performance is to be better than the present day Reduced Instruction Set Computing and Complex Instruction Set Computing(RISC & CISC).
The Itanium architecture achieves a more difficult goal than a processor that could have been designed with Ëœprice as no objectâ„¢. Rather, it delivers near-peerless speed at a price that is sustainable by the mainstream corporate market.
TODAYâ„¢S ARCHITECTURE CHALLENGES
The main challenges in todayâ„¢s architecture are the following:
Â¢ Sequential Semantics of the ISA
Â¢ Low Instruction Level Parallelism(ILP)
Â¢ Unpredictable Branches, Memory dependencies
Â¢ Ever Increasing Memory Latency, Ever increasing Memory
Â¢ Limited Resources(registers,memoy address)
Â¢ Procedure call,Loop pipelining Overhead
A program is a sequence of instructions. It has an implied order of instruction execution. So there is a potential dependence from instruction to instruction. But high performance needs parallel execution which in turn needs independent instructions. So independent instructions must be rediscovered by the hardware.
Consider the code:
add r1=r2,r3 add r1=r2,r3
sub r4=r1,r2 sub r4=r11,r2
shl r5=r4,r8 shl r5=r14,r8
Here though the compiler understands the parallelism within the instruction, it is unable to convey it to the hardware. So the hardware needs to rediscover the parallelism in the instructions.
LOW INSTRUCTION LEVEL PARALLELISM(ILP)
In present day programs branches are frequent. As a result code blocks are small. So parallelism is limited within the code blocks. Wider machines need more parallel instructions. So ILP across the branches need to be exploited. But when this is done some instructions can fault due to wrong prediction. In short branches are a barrier to code motion.
Branch predictions are not perfect. When wrong it leads to performance penalty. It is more if the instructions which went wrong consist of memory operations (loads & stores) or floating point operations. Also if exception on speculative operations, we need to defer it. This results in more book keeping hardware.
Usually load instructions are at the top of a chain of instructions. ILP requires moving these loads. Store instructions are also a barrier. Dynamic disambiguation has its limitations For it requires additional hardware and it adds to the code size if done in software.
Though the speed of A.L.U, decoders and other execution units have increased with time, the advances in technologies related to memories is not in pace with it. So even if the decoding and further execution of the instruction is fast ,the memory fetch which is needed prior to it takes time and leads to reduced pace of program execution. The cache hierarchy which reduces the memory latency has its limitations. It is managed asynchronously by hardware and helps only if there is locality. Also it consumes precious silicon area.
Small register space creates false dependencies. Shared resources like conditional flags and conditional registers force dependencies on independent instructions. Floating point resources are limited and not flexible.
PROCEDURE CALL & LOOP PIPELINING OVERHEAD
As modular programming is increasingly used the programs tend to be call intensive. Register space is shared by caller and calle. Call/return requires register save/restore.
Though loops are common sources of good ILP Unrolling/Pipelining is needed to exploit this ILP. Prologue/Epilogue causes code expansion. So the applicability of these techniques is limited.
IA-64 ARCHITECTURE PERFORMANCE FEATURES
Â¢ Explicitly Parallel Instruction Semantics
Â¢ Control/Data Speculation
Â¢ Massive Resources(registers, memory)
Â¢ Register Stack and its Engine
Â¢ Memory Hierarchy Management Support
Â¢ Software Pipelining Support
EXPLICITLY PARALLEL INSTRUCTION SEMANTICS
Here program is a collection of parallel instruction groups. The instructions have implied order and no dependence between instructions within a group. So high performance is obtained as independent instructions are explicitly indicated for parallel execution.
add r1=r2,r3 ;; add r1=r2,r3
sub r4=r1,r2 ;; sub r4=r11,r2
shl r5=r4,r8 ;; shl r5=r14,r8
consider the above code. Here the dependent instructions are differentiated from independent instructions by the compiler with the help of Itaniumâ„¢s unique instruction set architecture. The absence of semi colom( conveys the independence. So there is no need for the hardware to rediscover the available parallelism. Thus hardware can easily exploit parallelism.
As a result of predication of unpredictable branches are removed, and so misâ€œpredication penalties are eliminated. So compiler has a larger scope to find ILP.Basic block size increases as both then and else are executed in parallel. Thus predication results in increased speed of execution.
Traditional architecture IA-64
It allows execution of an instruction to be based on a previously determined condition, such as a runtime compare of two values. If the value is equal then the instruction could be executed. If the value is not equal then the instruction can be ignored without affecting program flow. Proper use of this facility removes one of the biggest bottlenecks todayâ„¢s programmers face on a IA-32 architecture ,ie. that of refilling the instruction pipeline after a branch. For example ,if you consider the source code:
The instruction flow can generally be written as:
1. Compare x to 4
2. if not equal go to line 5
4. go to line 6
6. //Program continues from here
Regardless of the value in x there is at least one break in the instruction flow, either on line 2 or 4.Also ,in a worst-case scenario based on past values of x and the modern CPUâ„¢s ability to do some runtime statistical analysis, the CPU may mistakenly guess a branch on line 2, when in fact there is none this time around. Under those circumstances, program flow would be interrupted twice in one pass, causing a huge penalty.IA-64â„¢s predication allows you to totally bypass this shortcoming in existing architectures by assigning the results of the compare operation to a predicate bit which can later be examined prior to executing an instruction and, based on the bitâ„¢s value, either allow or disallow the instructionâ„¢s output to be committed to memory. This is essentially the concept of predication. To use our example above, the same source code could be written using this IA-64 instruction flow:
1. Compare x to 4 and store result in a predicate bit(weâ„¢ll call it A)
2. if A==1;z=9
3. if A==0;z=0
As you can see, the ability to test the condition of A, which is really the result of the compare in 1,allows the instruction flow to never be interrupted. If the value of A matches the comparison condition(the predicate) the results are written to memory, otherwise theyâ„¢re ignored. In this example ,all three lines of code would be executed sequentially without an interruption in program flow, but only the results from 2 would be committed to memory because thatâ„¢s the only predicate condition that matched the result of the compare in 1.Additionally,once that A bit is set it can be tested again and again in subsequent code until the optimizing compiler or the Assembly programmer, recognize it needs to be physically tested again because the result mightâ„¢ve changed. Predication can be considered as the greatest aspect of IA-64â„¢s design.
Traditional architecture IA-64
Code speculation is defined by the Intel as the compiler concept Control Speculation where an instruction or a sequence of instructions is executed before it is known that the dynamic control flow of the program will actually reach the point in the program where the sequence of instructions is needed. This means IA-64 can physically be told to execute instructions in advance, if possible, and keep all results from those instructions stored in a temporary area that is not written to main memory until such time as it becomes valid to execute that sequence of instructions. This has the benefit of removing latency in program flow by looking ahead to whatâ„¢s coming up. It can also work with speculative data loads, providing an absolutely incredible potential for data processing speedup under the right conditions. Unfortunately, it also has the potential of raising exceptions that would not otherwise be raised(because the dynamics of the runtime program flow never really ended up executing those instructions).But IA-64 provides or this and sets up an internal condition which defers any exceptions rose under speculative execution until such time as that code is actually executed. If the code is never executed the results are simply discarded. This is just one more brilliant feature incorporated into the IA-64 architecture.
Traditional architecture IA-64
stored by compiler
Data Speculation is defined by Intel as a sequence of instructions which consist of an advanced load, zero or more instructions dependent on the value of that load, and a check instruction which serves to validate whether or not the speculation was successful. This means any sequence of stores and loads can be speculatively issued in advance of their being needed ,with the validity of that speculation being determined at a point much later in the instruction flow. This has the all-important benefit of keeping the memory bus fully utilized by moving memory reads/writes away from their required physical location in the program flow to a point where, for example ,no memory access would otherwise occur. This is of obvious benefit when it can be statistically shown that the majority of the time the speculation will be successful. Under a worst case scenario, the speculation will fail and the memory access will simply be issued at the point in the program flow where it is actually needed. There should be no question this can speed things up greatly under the right conditions and is another reason certain benchmarks appear to run much faster on IA-64.
RSE(REGISTER STACK ENGINE)
GR stack reduces need for save/restore across call. Also Itanium has a procedure stack frame of programmable size(0 to 96 registers).This mechanism is implemented by renaming registers. RSE automatically saves\restores registers without software intervention. It provides the illusion of infinite physical registers. RSE may be designed to utilize unused memory bandwidth to perform register spill and fill operations in the background.
MASSIVE MEMORY RESOURCES
Â¢ 8 billion Gigabytes accessible
Â¢ Both 64 bit and 32 bit pointers supported
Â¢ Both Little Endian and Big Endian order supported
Â¢ 128 64-bit general purpose registers, named GR0-GR127.GR0 always reads 0 when sourced as an operand.
Â¢ 128 82-bit floating point registers, named FR0-FR127.FR0 always reads +0.0 when sourced,FR1 always reads +1.0 when sourced. Format consists of 1-bit sign|17-bit exp|64-bit explicit one mantissa.
Â¢ 64 1-bit predicate registers, named PR0-PR63.PR0 always reads 1.
Â¢ 8 64-bit branch registers, named BR0-BR7.Used to hold indirect branching information.
Â¢ 8 64-bit kernel registers, named KR0-KR7.Used to communicate information from the kernel to an application.
Â¢ 64-bit CFM register, Current Frame Marker. Used for stack-frame operations.
Â¢ 64-bit IP, Instruction Pointer .Holds pointer to current 16-byte aligned bundle in IA-64 mode, or offset to 1-byte aligned instruction in IA-32 mode.
Â¢ NaT and NatVal 1-bit registers, named Not-a-Thing and Not-a-Thing-value. These are used under speculative execution to indicate deferred exceptions associated with the register. There is one Nat bit for every GR register, and one NaTVal bit for every FR register.
Â¢ There are several other 64-bit registers with operating system-specific, hardware-specific, or application-specific uses covering hardware control and system configuration.
Specifications of some registers
1. Process status register (PSR)-64 bit register that maintains control information for the currently running IA-64 or IA-32 process.
2. Control Register(CR)-This register name space contains several 64-bit registers that capture the state of the processor on an interruption, enable system wide IA-64 or IA-32 features, and specify global processor parameters for interruptions and memory management.
3. Interrupt Registers- These registers provide the capability of masking external interrupts, reading external interrupt vector numbers, programming vector numbers for internal processor asynchronous events and external interrupt sources.
4. Interval Timer Facilities-A 64-bit interval timer is provided for privileged and non-privileged use and as a time base for performance measurements.
5. Debug break point registers(DBR/IBR)-64 bit data and 64 bit instruction break point register pairs (DBR/IBR) can be programmed to fault on reference to a range of virtual and physical address generated by either IA-64 or IA-32 instructions. The minimum number of DBR register pairs is 4 in any implementation.
6. Performance Monitor Configuration /Data Registers(PMC/PMD)- Multiple performance monitors can be programmed to measure a wide range of user, operating system ,or processor performance values. Performance monitors can be programmed to measure performance values from either the IA-32 or IA-64 instruction set. The minimum number of generic PMC/PMD register pairs in any implementation is 4.
7. Banked General Registers-A set of 16 banked 64 bit general purpose registers,GR16-GR31, are available as temporary storage and register context when operating in low level interruption code.
8. Region Registers(RR)-An eight 64 bit region registers specify the identifiers and preferred page sizes for multiple address spaces.
9. Protection Key Registers(PKR)-At least sixteen 64-bit protection key registers contain protection keys and read, write, execute permissions for virtual memory protection domains
10. Transition Look-aside Buffer(TLB)-Holds recently used virtual to physical address mappings. The TLB is divided into Instruction (ITLB),Data (DTLB),Translation Registers(TR) and Translation cache (TC) sections. Translation Registers are software-managed portions of the TLB and the processor directly manages the Translation cache section of the TLB.
IA-64 SYSTEM ENVIRONMENT
IA-64 (IA stands for Intel Architecture) architecture features two full operating system environments:the IA-32 System Environment supports IA-32 operating systems, and the IA-64 System Environment g systems. The architectural model also supports a mixture of IA-32 and IA-64 application code within an IA-64 operating system.
The system environment determines the set of processor system resources seen by the operating system. The choice of the system environment is made when an IA-64 processor boots, and is described below:-
IA-64 Processor Boot Sequence
IA-64 System Environment IA-32 System Environment
yes FirmCall to PAL_ENTEER_IA_32_ENV
Figure shows the defined boot sequence for IA-64 processor, which power up in 32-bit Real Mode,IA-64 processor power up in the System Environment running an IA-64 code. Processor Initialization, testing and platform initialization/testing are performed by IA-64 processor firmware. Mechanisms are provided to execute Real Mode IA-32 boot BIOSs and device drivers during the boot sequence. After the boot sequence ,a determination is made by boot software to continue executing in IA-64 operating system environment(for example to boot an IA-64 operating system) or to enter the IA-32 operating environment through the PAL_ENTER_IA_32_ENV firmware call.
IA-64 System Environment Overview
The IA-64 environment is designed to support the execution of IA-64 operating systems running IA-32 or IA-64 applications.IA-32 applications can interact with IA-64 operating systems ,applications and libraries within this environment. The operating system and the user level software can execute both IA-32 application level code and IA-64 instructions. The entire machine state, including all IA-64 resources,IA-32 general registers and the floating â€œpoint registers, segment selectors and descriptors is accessible to IA-64 code. As shown in figure below all major IA-32 operating modes are fully supported.
In the IA-64 system environment ,IA-64 defined operating system resources supersede all IA-32 system resources. Specifically the IA-32 defined set of control, test, debug, machine check registers, privilege instructions, and virtual paging algorithms are replaced by the IA-64 system resources. When IA-32 code is running on an IA-64 operating system, the processor directly executes all performance critical but non-sensitive IA-32 application level instructions. Accesses to sensitive system resources (interrupt flags, control registers, TLBs, etc)are intercepted into the IA-64 operating system. Using this set of intervention hooks, an IA-64 operating system can emulate or visualize an IA-32 system resource, or device driver.
The information technology industryâ„¢s term RAS is one that applies directly to Itanium. ËœRASâ„¢, or ËœReliability-Availability-Serviceabilityâ„¢ provides an excellent example of the benefits that Itanium brings to clients. In each case, Itanium can provide a benefit that is either unique or best in its class compared to less advanced processors.
ËœReliabilityâ„¢ refers to the ability of the hardware to avoid failing. With the Itanium Processor family, this ability is built directly into the processor. The prime example of the improved reliability of the processor is the built-in Ëœerror correcting memoryâ„¢. A change in the bit means that the value in the memory has also been altered. The error correcting memory will fix the problem on the fly guarding against this effect. This is because error correction introduces of Ëœparity checkâ„¢ that can tell whether a given bit should be Ëœonâ„¢ or Ëœoffâ„¢, and even fix the piece of data.
A system with 100% ËœAvailabilityâ„¢ is a system that is always up and never down. The main reason systems tend to crash and go down is mainly due to Ëœhardâ„¢ and Ëœsoftâ„¢ errors. A Ëœhardâ„¢ error implies something is physically changed on the system, or a piece of hardware crashes, freezes, or burns up.
In Ëœsoftâ„¢ errors a cosmic ray or electrical noise on a bus will unintentionally and randomly reset a data bit. But the parity and error correcting code circuits(ECC) of the Itanium processor will actually fix these errors as they are detected and keep the userâ„¢s computing environment safe. The on-chip parity checks and ecc will detect and correct both hard and soft errors.
This is a capability that has been built into the architecture. In a multi-processor situation you can turn off one processor and substitute in a new one. The ability to service the machine while it is still running reduces your downtime even further.
Some of the features that this processor brings to the follow below:
Â¢ Floating-point performance for compute intensive applications
Â¢ EPIC technology for maximum parallelism &HW\SW synergy
Â¢ Scalability from 1-way to128-way+
Â¢ 64-bit addressing and high bandwidth
In modern Processors, including Itanium, a multiplicity of arithmetic-logic or floating-point on-chip units execute several instructions in parallel. Ideally, increasing the number of execution units should increase the number of extra instructions per clock cycle proportionally. But conventional processors also needs a lot of extra on-chip circuitry to schedule and track the instruction progress, which takes up valuable space, consumes power and add steps to the execution process. As a result only a slight improvement in the number of instructions per clock cycle occurs when the number of execution units are increased. Instead EPIC architects use a compiler to schedule instructions.
An excellent scheduler ,it makes parallelism explicit to the processor. It bundles instructions into 128-bit packets containing up to three instructions plus information about the interdependencies. Less scheduling and tracking circuitry is needed on the chip and the extra information in each bundle allows the architecture to be scalable so that programs compiled for todayâ„¢s itanium systems will not need recompilation for future generations of the chip.
BENEFITS OF ITANIUM PROCESSORS IN DIFFERENT PLATORMS
*How Will I Benefit if I Run a RISC-Based System
Enterprises that run RISC-based systems gain an immediate benefit from the switch to an Itanium-based platform. The lower hardware costs and multi-vendor OS strengths of the new industry-standard architecture,
Explicitly Parallel Instruction Computing (EPIC), provide for the following benefits:
Â¢ Multi-OS support
Â¢ Lower overall Cost of Ownership for enterprise IT
Â¢ Assurance of leading performance and scalability over the long-term
*How will I Benefit if I Run an IA-32 Based System
IA-32 based system users will see immediate performance gains when taking on more complex workloads and processing large amounts of data. Areas that are less sensitive to performance can transition to the new architecture on an as-needed basis. Organizations that move to an Itanium â€œbased platform can address current performance issues points today and gain familiarity with architecture that will be able to keep up with scalable demands in the near and intermediate future. These demands include:
Â¢ Greater memory addressability
Â¢ More complex applications and computing environments
Â¢ Secure web server transactions
Â¢ Computer aided design such as Mechanical Analysis
Â¢ Very large memory databases
THE INTEL ITANIUM 2 PROCESSOR
The Intel Itanium 2 Processor with 6MB L3 cache is uniquely architected for demanding enterprise and technical applications. Itanium 2-based platforms enable businesses and organizations to maximize their return on investments by delivering industry leading performance at generally lower cost and with greater choice than proprietary RISC technologies.
Intel Itanium 2 Processor Features
Why choose Systems Based on the Intel Itanium 2 Processor with 6M L3 cache
*Record Performance: The Itanium processor enables industry-leading performance. Currently, Itanium 2 based systems hold number-one results running a series of Enterprise and HPC applications.
*Solutions availability: Itanium 2 processors with 6M L3 cache are supported by a rich ecosystem of highly scalable, open-standard 64-bit datacenter solutions from leading vendors on over 40 platforms, more than 5 operating systems and over 300 applications.
*Uniquely designed for the enterprise: Platforms based on the Intel Itanium 2 processor with 6M L3 cache provide leading enterprise performance, extending Intel volume economics to the most data-intensive, business critical applications.
Itaniumâ„¢s ability to handle just about any operating system that is run on it makes it a natural fit for todayâ„¢s mixed network environments. Itanium architecture today includes world-class capability for targeted applications, including:
Enterprise Resource Planning, Supply Chain Management
Mechanical Computer Aided Engineering(MCAE),Intensive Custom Applications(financial, petroleum, others)
The Itanium architecture was designed to be the new industry standard in high performance processor architecture for the next twenty years. The Itanium processor captures the best-in-class application performance for technical and enterprise computing out of the box today. However, given the continued development of chips and compilers for this unique architecture is also bright.
The Itanium Processor starts out with a strong price/performance ratio and is designed to take advantage of scalability gains. This is assisted by broad industry support led by both HP and Intel.
The Itanium architecture was developed to meet and exceed future performance and growth needs of enterprise business, technical, and scientific users with greater flexibility and future headroom. The idea was to create an architecture capable of greater speed and also unbeatable price-performance.
The Intel Itanium Processor is faster than most of the present day competition. And, with future compiler improvements and newer chip designs, it will outplace all other existing architecture.
No matter if you run RISC or IA-32 based systems ,youâ„¢ll still able to reap performance gains from Itanium-based systems.
An Itanium-based platform also provides superior performance in all three areas of ËœRASâ„¢:â„¢ Reliability-Availability-Serviceabilityâ„¢.
The Itanium processor uses EPIC, or explicitly parallels instruction computing architecture. This allows a system to go from one instruction per cycle to 6 or even more instructions per cycle.
Investment protection was another goal of Itanium-based solutions. The triple protection that Itanium-based systems offer is for legacy software, legacy hardware, and legacy data. This is due in part to Itaniumâ„¢s ability to work with almost any operating system and application.
Enterprise computing is an ideal place for Itanium power. By improving upon capabilities of todayâ„¢s architectures, Itanium can ensure flexibility and choice in the enterprise environment.
IA-64â„¢s deign is fluid. Its operational characteristics are entirely controlled by the compiler or assembly programmer. It doesnâ„¢t engage in any of the automatic speedup mechanisms that are present in Intelâ„¢s IA-32 architecture. It is an obedient servant of the programmer. Itanium is a machine capable of achieving levels of true greatness that are directly commensurate with the programmers abilities. Because the EPIC architecture is new for both Intel and HP, software written for Intelâ„¢s Pentium and HPâ„¢s PA-RISC machines need to be execute on Itanium platforms. To this end Intel included a small engine in the new design to execute the programs written for Pentium platforms. HP used software similar to code morphing method invented by Transmeta.
Itaniumâ„¢s 64-bit architecture is crucial to Intelâ„¢s Invasion of high-end workstations and servers. A 64-bit data path guarantees a vastly larger addressable memory space. The 32-bit architecture of Intelâ„¢s Pentium can directly access upto 4GB of memory only. The 64-bit architectures can directly address more than 16 Exa-bytes(roughly 10^18 bytes).
4. INTEL 80186,80286,80386 AND PENTIUM PROCESSORS BY RECTOR RUSSELL AND GEORGE ALEXY.
I express my sincere gratitude to Dr. Agnisarman Namboodiri, Head of Department of Information Technology and Computer Science, for his guidance and support to shape this paper in a systematic way.
I am also greatly indebted to Mr. Saheer H.B. and Ms. S.S. Deepa, Department of IT for their valuable suggestions in the preparation of the paper.
In addition I would like to thank all staff members of IT department and all my friends of S7 IT for their suggestions and constrictive criticism.