Low-k dielectrics are the very latest path breaking development in the field of Integrated Electronics. It is well on its way replacing the Al / SiO2 interconnects with the help of copper in CMOS fabrication of IC Chips. The CMOS technology has an in-built coupling capacitance which increases the time delay, thereby reducing associated processing speeds. This was compensated by reducing the thickness of the Al / SiO2 interconnects. There is a limit to the reduction in thickness after which an inverse effect is seen. This is where Cu / low-k dielectric interconnects come into the picture. In this case, the processing speed and hence the device performance is improved by reducing the RC delay. Low-k dielectrics are materials which have a dielectric constant less than 3. Air has the least k of 1, and so is used for production of low-k dielectric materials.
In this fast moving world time delay is one of the most dreaded situations in the field of data communication. A delay in the communication is as bad as loosing the information, whether it is on the internet or on television or talking over a telephone. We need to find out different ways to improve the communication speed. The various methods adopted by the communication industry are the wireless technology, optical communications, ultra wide band communication networks etc. But all these methods need an initial capital amount which makes all these methods cost ineffective. So improving the existing network is very important especially in a country like INDIA.
The communication systems mainly consist of a transeiver and a channel. The tranceiver is the core of all data communications. It has a very vast variety of electronic components mostly integrated into different forms of IC chips. These ICs provide the various signal modifications like amplification, modulation etc. The delay caused in these circuits will definitely affect the speed of data communication.
This is where this topic LOW-k DIELCTRICS becomes relevant. It is one of the most recent developments in the field of integrated electronics. Mostly the IC s are manufactured using the CMOS technology. This technology has an embedded coupling capacitance that reduces the speed of operation. There are many other logics available like the RTL,DTL,ECL,TTL etc . But all these other logics have higher power consumption than the CMOS technology. So the industry prefer CMOS over other logics .
Inside the IC there are lots of interconnections between points in the CMOS substrate. These refer to the connection between the different transistors in the IC. For example , in the case of NAND LOGICS there are lots of connections between the transistors and their feedbacks. These connections are made by the INTERCONNECT inside the IC . Aluminum has been the material of choice for the circuit lines used to connect transistors and other chip components. These thin aluminum lines must be isolated from each other with an insulating material, usually silicon dioxide (SiO2).
This basic circuit construction technique has worked well through the many generations of computer chip advances predicted by Moore's Law1. However, as aluminum circuit lines approach 0.18 mm in width, the limiting factor in computer processor speed shifts from the transistorsâ„¢ gate delay to interconnect delay caused by the aluminum lines and the SiO2 insulation material. With the introduction of copper lines, part of the speed limit has been removed. However, the properties of the dielectric material between the layers and lines must now be addressed. Although integration of low-k will occur at the 0.13mm technology node, industry opinion is that the 0.10mm generation, set for commercialization in 2003 or 2004, will be the true proving ground for low-k dielectrics because the whole industry will need to use low-k at that line width.
As already mentioned, interconnects are the connections made inside the IC to send the data from point to point. These connections almost take up the 90% of the bulk of the IC. So these connections should have the maximum resistance. The interconnects are not a continuous piece of metal. They are layers of metal separated by insulators. These insulators help to prevent the message being coupled into other layers. Due to the resistance of the metal and the capacitance of the insulator there occur a delay in sending data through these interconnects. This delay is called the RC delay. These cause major havoc Ëœcross-talkâ„¢. This is the spreading of the information given to a particular point. This reduces the processing speed of the IC.
Aluminium is used as the interconnect in the present day chips. The insulator used is SiO2. But aluminium has high resistivity that will increase the time delay. The other major metals used are gold, silver, copper etc. But the Au and Ag are not cost effective. Also all these three elements have bad reactions with the SiO2, which will change the physical properties of the SiO2.
So to reduce the RC delay Cu is selected mainly for its low resistance and better availability. These are the major advantages and disadvantages of selecting Copper.
Copper has 40% lower resistivity than aluminum (1.7 vs 2.7 Ã‚Âµohm - cm).
At 0.13 micron size, the RC delay for copper is half of AL when used with low-k materials.
Copper allows thinner, more closely spaced wires than previous technologies.
Used in conjunction with low-k dielectrics the number of metal layers can be cut in half, reducing manufacturing costs.
Copper has superior resistance to electron migration to aluminum.
Copper allows a reduction in power consumption without a reduction in chip speed.
For reliable Cu integration with existing backend oxide dielectrics, Cu must be encapsulated with barrier materials.
In the presence of an electric field at temperatures as low as 150Ã‚Â°C, positive Cu ions (Cu+) drift rapidly through oxide to degrade field isolation, induce dielectric leakage, and even degrade active devices.
Copper is more difficult to etch, requiring manufacturers to adopt new processes.
The technology concerned here is the thin film technology. In this technology the size of the interconnect varies from 1A0 to 1micron. The size of the interconnect or width is referred to as the pitch size. At the technology less than .3micron the effect of low k dielectric insulators is must for optimum result.
The capacitance in the circuit is main reason for the reduction of speed in the CMOS technology. On the above the interconnect capacitance also cause the delay. These are some main points corresponding to the capacitance inside the IC.
When interconnect space is less than 0.3Ã‚Âµm, the interlayer capacitance is very small compared to the total capacitance.
At sub-0.25Ã‚Âµm feature sizes, 90% of the total capacitance is dominated by line-to-line capacitance.
Since the capacitance is proportional to k, a reduction in k leads to lower capacitance and RC delay.
THE NEED FOR NEW DIELECTRICS
Approaching 0.18 m line widths, interconnect delay, also called RC delay, increases. A simple model can be used to explain this phenomenon, and a picture of this model is shown in Figure 3. For an interconnect line of length L, the total resistance R of the line can be written as shown in Equation 1.
In this equation, is the resistivity, P is the pitch or line spacing and T is the thickness of the line.
For capacitance, there are two capacitance factors: the lateral line to line capacitance CLL; and the vertical layer to layer capacitance CV. The total capacitance can be written as shown in Equation 2.
In this equation, k is the relative dielectric constant, and 0 is the permittivity of vacuum. Combining these two equations yields Equation 3 for the total RC delay.
Equation 3 shows that several chip geometry drivers (conventional thoughts to decrease P and T) are forcing RC delay to increase. Also, increasing system complexity and die sizes are driving up L as well4. For these reasons, decreasing RC can only be accomplished by changing and k. Figure 2 provides a graphical view of the effect of changing line and dielectric materials. This figure shows that without switching to Cu and low-k materials, the aggregate delay (interconnect plus gate delay) will increase significantly and impact system performance. However, addressing the benefits of Cu is not the purpose of this Applications Note. Only low-k materials, specifically spin-on materials, will be discussed.
Choosing a New Dielectric Material
Any process change in the semiconductor industry is difficult, but choosing a new dielectric material has been (and continues to be) an exercise in trying to find a low-k dielectric film with electrical, thermal and mechanical properties comparable to or better than those of SiO2 (e.g., good hardness, adhesion, etc).
At this time, there is no standard for these new materials and no material has yet to gain an advantage. Significant differences in applications and chip architecture may preclude such a standard. However, Ting8 and others were able to generate a generic list of the most critical dielectric requirements. This list is shown in Table 1.
Although Table 1 contains many properties, several of the more important properties of a dielectric include the following:
Good thermal stability and low coefficient of thermal expansion. These properties are needed to prevent both damage to the film or property changes during subsequent thermal processes.
An isotropic dielectric constant of less than 3.0. Also, when combined with barrier layers, the effective dielectric stack should have an effective k of less than 3.0. Typically, a barrier dielectric material is needed below and above the main dielectric material. This creates a dielectric stack, largely determining the line-to-line capacitive coupling and RC interconnect delay. It does no good to combine the low-k dielectric with highly capacitive barrier layers since having a low effective k is the very reasons for adopting a low-k material in the first place.
Good adhesion. Adhesion is particularly key, especially for organic spin-on materials that often do not adhere well to standard CVD oxide and nitride films, or barrier metals including Ti, TiN, Ta and TaN. This is a serious issue as the chemical mechanical planarization (CMP) process can cause deformation or removal of dielectric layer during damascene or dual damascene processing.
Etch and Strip resistance. The potential for via poisoning comes from etching and resist removal. Etch processes have to be optimized for profile control and, importantly, zero damage. The stripping process replaces the traditional oxidizing chemistry with a hydrogen-based reducing chemistry.
Commercial availability and low cost of ownership.
Current Spin-on Low-k Dielectric Material Options
Finding polymers with low dielectric constants is a relatively easy task. However, finding those with the required chemical, mechanical, electrical and thermal properties for use in integrated circuit applications is more difficult. Much effort has gone into these searches and Table 2 provides a list of industry recognized dielectric material candidates for the 0.13m and 0.1m technology nodes.
Although all of these may be suitable for the 0.13m technology node, not all are suitable for the 0.1m node. For some materials, the k value is not low enough, while for others there are properties of the material that eliminate it as an option. The following sections discuss the advantages and disadvantages of each type of spin-on material.
Polyimides are high viscosity (typically greater than 3,000 centipoise) engineering polymers that are currently used in a wide variety of microelectronic applications (e.g., protective overcoats, flip chip bonding applications, alpha particle barriers, etc.). Polyimides are used for these applications as they exhibit excellent mechanical, thermal, and electrical properties when compared to most other organic or polymeric materials. As shown in Figure 3, polyimides are formed by the imidization (condensation reaction) of polyamic acids. Varied properties can be obtained depending upon the aromatic compounds in the polyamic acid. For use as a low-k material, polyimides can have the following advantages:
good thermal stability;
and a low dielectric constant (even lower with fluorinated polyimides)
However, there are two main issues with polyimides. One is moisture absorption. Although fluorinated polyimides have slightly less moisture uptake, standard polyimides can absorb several percent of moisture. The other issue is dielectric constant anisotropy. Studies have shown that the within plane dielectric constant of both fluorinated and non-fluorinated polyimides is significantly higher than the out-of plane dielectric constant. This anisotropy makes these materials unsuitable for low-k applications between metal lines.
B-staged polymers like CYCLOTENE from Dow Chemical are currently used in production for GaAs interlayer dielectric (ILD) applications. B-staged polymers are thermoset resins formed from a prepolymer of divinyl siloxane bisbenzocyclobutene (DVS-BCB). This reaction is shown in Figure 6. One difference from polyimide is that BCB does not evolve water during crosslinking. After cure, the crosslinked BCB polymer has low moisture uptake and a low, isotropic k value. The main disadvantage of BCB is the thermal stability of the cured film.
When exposed to air at even low temperatures (150C to 300C), the rate of weight loss well exceeds the 1% target for low-k dielectrics. Also, air exposure increases the dielectric constant and can increase moisture uptake and yield cracked films16. Using an oxide hard mask can increase the stability of BCB to 390Ã‚Â°C. It has also been integrated with TiN barrier deposition, Cu fill by MOCVD and Cu CMP in a single damascene structure.17 To work around some of these issues, fluorination of BCB was studied. Perfluorocyclobutane (PFCB) is an aromatic ether thermoset that has pendant perfluorovinyl ether groups
This material has improved thermal stability over DVS-BCB and a lower dielectric onstant (k = 2.24). However, the addition of fluorine can cause interface issues with metals like Cu, Ta and Ti18. In Cu damascene structures in particular, fluorine readily attacks tantalum-based barriers, leading to volatile TaF2 formation and loss of low-k/barrier adhesion. This remains a key impediment to damascene integration of fluorine-based low-k materials with copper. For all of these reasons, PFCB has not been considered for future use.
SiLK is another polymer from Dow Chemical that has garnered significant interest in the semiconductor industry. As shown in Figure 8, SiLK contains neither fluorine nor silicon. It is highly aromatic, and it has an isotropic k with very high temperature stability. Dow Chemical reports that SiLK formulations fit both copper/damascene and Al/W applications. A recent study by Fujitsu demonstrated one of the first integrations of organic polymers, SiLK and FLARE2.0, in a two-level Cu damascene structure. Chosen due to their high thermal stability, SiLK and FLARE demonstrated little change in k value after five-hour anneals at 425Ã‚Â°C. The process used TiN barrier layers, Cu and tungsten plugs, rather than a dual-damascene approach. An oxide cap acted as hard mask and CMP stop.
Poly(arylene ethers) (PAE)
Poly(arylene ethers) are another class of organic spin-on polymers. As shown in Figure 9, the polymerâ„¢s properties can be changed by modifying the chemical structure of the aromatic precursor or bis-phenol. For reasons previously stated (e.g., barrier metal adhesion), these materials are not fluorinated. These materials have good properties for use in a dielectric application as indicated below:
Low outgasssing after cure.
Thermally stable with low moisture uptake and good solvent resistance.
Cured films have excellent adhesion to both SiO2 and metals
Anisotropic k, but it is relatively high at 2.8.
FLARE from Honeywell and VELOX from Schumacher are two of the better- known PAEs. Recent studies have shown the integration of FLARE into dual damascene Cu structures and multi-layer TEOS and nitride stacks.
Inorganic polymers are usually built on an O-Si-O backbone. These materials are more like SiO2 than other organic polymers. Thus, they have a perceived advantage over other polymers. Other advantages of these materials are that they typically have higher Tgâ„¢s, hardness and toughness. However, the main disadvantage for these siloxane polymers is that they are also brittle. This makes them susceptible to damage during CMP.
Hydrogen silsesquioxane (HSQ) can form either a cage or a ladder structure. The ladder structure is shown in Figure 10 while the cage form is shown in Figure 11. HSQ was first implemented in DRAM and other devices, not because of its low dielectric constant (2.9) but to simplify and reduce the cost of processing26. Since its early use, HSQ has gradually gained acceptance as a low-k spin-on material27. One such commercial offering is FOx(Flowable Oxide) from Dow Corning. However, one of the main drawbacks of HSQ is its thermal stability. Processing at temperatures above 400C increases the dielectric constant near that of SiO2.
Methyl Silsesquioxane (MSQ) is similar to HSQ, but methyl groups replace the hydrogen (see Figure 12). The main difference between HSQ and MSQ is that MSQ does not decompose at temperatures above 400C. Also, MSQ films tend to have lower stress and higher resistance to cracking when compared to HSQ. Many companies are working on MSQ materials including Hitachi and Honeywell.
Honeywellâ„¢s HOSPis a spin-on hybrid MSQ-organic polymer with a dielectric value of 2.5. HOSP contains high levels of carbon doping. Although the cagelike structure of HOSP has more internal stress than traditional dielectric materials, the incorporation of a critical level of Si-C bonds results in more stable k values. This results in a polymer that is more robust due to increased film density and Si-C bond stabilizing effects.
PTFE is used in many semiconductor applications such as wafer carriers, filters, high-purity piping and wet benches. W.L. Gore and Associates is in prototype production of a PTFE spin-on nanoemulsion with k of 1.9. The SPEEDFILMmaterial is an aqueous emulsion containing sub-20nm PTFE particles and surfactant.31 This material is non-porous, oxidation resistant, and inherently hydrophobic. The film demonstrates good thermal stability at up to 400Ã‚Â°C and has a 460Ã‚Â°C decomposition temperature32. SPEEDFILM is not commercially available yet, but it has undergone adhesion testing, etching, CMP studies as well as electrical characterization and is being integrated into 0.15 Ã‚Âµm devices.
The ideal low-k dielectric material is no material at all. As shown in Table 2, air gaps have the lowest k-value at 1, but they also suffer from low breakdown voltage, low strength and low thermal conductivity. Therefore, the next best material is one with a reduced density, e.g. porosity. As a result, there are many companies working on adding porosity to dielectric materials.
Original formulations of SiLK are limited to k = 2.65, but Dow Chemical and IBM are addressing the extendibility of SiLK through an $18 million Advanced Technology Program grant from the National Institute of Standards & Technology. The goal of the program is to develop a porous (closed cell, 10nm pore diameter) version of SiLK with a dielectric constant of 1.5 to 2.0 for 0.1m semiconductors. Initial results have been promising33. Porous PAE materials have also been developed. Porous FLARE has delivered a k value of 1.9- 2.2 with good adhesion.
A single layer Cu damascene integration was completed, but Youngâ„¢s modulus was reduced by 50% and there has been some decrease in thermal stability and plasma resistance due to the higher exposed surface area.34 Xerogels and aerogels are another classification of porous material. Aerogels are highly porous solids formed by replacement of a liquid in a gel with a gas. This process involves supercritical extraction of a solvent(s) so that there is little shrinkage. On the other hand, xerogels are formed from a gel by drying it with unhindered shrinkage. These nanoporous silica coatings typically have a dielectric constant value between 1.0 and 3.0, depending upon the cure process.
NANOGLASS, from Honeywell, is based upon TEOS. Texas Instruments reported process feasibility using NANOGLASS in Al and single Cu damascene structures. Using 0.3 Ã‚Âµm metal lines, the Cu/NANOGLASS devices provided a 36% reduction in capacitance for lines of equal resistance and a 46% decrease in resistance for interconnects of equal capacitance. Hightemperature testing of NANOGLASS films reveals a stable k of 2.0 in an uncapped film after repeated thermal cycling to 500Ã‚Â°C.
Other nanoporous films can be formed via a two-phase controlled nanophase eparation of a blend, hybrid or copolymer system. Porosity is controlled by selective removal of sacrificial components. IBM is characterizing porous organosilicates (nanofoams) with k values of < 1.7 at <40% porosity. These materials demonstrate high thermal stability and process simplicity. These nanoporous inorganic-organic hybrids are created through the vitrification of low molecular weight silsesquioxane (MSQ) in the presence of highly branched thermally labile aliphatic polyesters of controlled molecular weight and architecture.
The thermally labile pore generator decomposes by heating to 350-400Ã‚Â°C to leave behind pores in the inorganic oxide. The combined structure contains closed-cell pores in a hydrophobic matrix, minimizing moisture absorption. XLKis from Dow Corning and is based upon HSQ. These pores, made by boiling out a solvent during a cure step, lower the dielectric constant of HSQ significantly-to between 2.0 and 2.5, depending on pore size. Also, ammonia treatment has been found to have a crucial influence on film characteristics (hydrophobicity and mechanical properties)36. In addition to this material, other materials under development are JSRâ„¢s LKD and Catalyst and Chemicalsâ„¢ IPS.
MesoELKfrom Schumacher involves spin-on deposition of a TEOS-based mesoporous material. The resulting film has a highly organized pore structure with good thermal stability. The mesoporous films potentially offer simplified processing and improved mechanical strength relative to conventional xerogel approaches.
How much porosity is needed
Now that so many companies are making porous materials, a key question is how much porosity is needed. Unfortunately, the percentage of porosity needed for low-k dielectrics is not an absolute number that can be applied across all materials. The porosity depends upon many factors such as pore diameter, microstructure and thickness. In addition, one of the more important factors is the choice of the matrix (assuming that k of the pore is 1). Although Bergman developed a rather sophisticated theory based upon the dispersion of pores in a matrix, a simpler model of the effect of porosity on dielectric constant can be used. In the case where k of the pore is less than that of the bulk material, the Maxwell-Garnett model37 can be used as shown in Equation 4.
In this model, subscript P refers to the pore, M refers to the bulk material, and ke is the effective dielectric constant of the compound material. Solving Equation 4 results in the following expression for the dielectric constant of the compound material (Equation 5):
Using this equation, we can then compare the porosity needed depending upon the starting k value of the matrix material. As shown in Figure 11, for a film with a matrix k of 4.0, 80% porosity is needed to reach an effective k of 1.5. However, for materials with lower matrix k values (2.65 and 1.9), it only takes 60% and 40% porosity to reach an effective k of 1.5. Recent reports have indicated that these results are in reasonable agreement with experimental measurements on MSQ and oxide porous films.40,41 Naturally, one would assume that introducing 80% porosity into SiO2 or 60% porosity into SiLK would be a reasonable solution to interconnect delay problems (assuming that you could make a heavily porous SiO2 film). However, this is typically not a viable solution as there can be significant issues with creating any porous films, such as:
Important mechanical properties (e.g., Youngâ„¢s modulus, tensile strength, hardness and fracture toughness) all scale inversely with porosity.
Thermal conductivity (heat dissipation) scales inversely with porosity.
The pores should be of the closed cell type (not open cell) to prevent crack propagation and moisture uptake.
The pore size distribution should be narrow to ensure that the bulk dielectric constant is homogeneous and isotropic.
Although these issues are not catastrophic, choosing a material(s) will require trade-offs between the dielectric constant and these properties. The resulting film properties will then impact the way that semiconductors are manufactured and interconnected. Most notably, wirebonding and CMP methodologies will have to be optimized to handle the decrease in hardness and toughness. Fortunately, strategies such as reinforcing architectures (e.g., sea of vias), B GA bonding and ceramic packages are available.
Figure 13. More porosity is needed to reach the same effective k value with higher dielectric constant matrix materials.
There deposition of the materials are very important in IC fabrication. The different methods are
Low-k materials can be deposited either by spin-on
CVD (chemical vapor deposition) methods.
The best low k material found is the porous materials. Porous materials are typically spun on. The different steps in the production of these porous materials are given below.
Controlled evaporation of solvent provides the desired pore structure.
Baking of the material is normally done in a batch furnace.
Bake temperature is typically between 350Ã‚Â°C - 400Ã‚Â°C.
Advantages of Spin-on Deposition
The various advantage of spin on deposition are given below:
SOD processes use deposition equipment that is less expensive than CVD process equipment.
One SOD coater/track can be used to deposit a much wider variety of viable low-k materials than any single CVD tool.
Provides a lower risk investment for future extendibility as technology advances.
Spin-on dielectric materials have high crack resistance.
Will CVD be replaced
CVD applied SiO2 has been a valuable dielectric for many years, and although a significant amount of CVD infrastructure exists, eventually spin-on may replace CVD as the process of choice. At this time, CVD materials and processes are not extendable to k values below 2 (see Table 2). Below 2, porosity is needed to create air gaps, and porosity cannot be introduced into CVD materials, as they aren't applied in the liquid phase. Nanoscale porosity can be imparted through the use of larger organic groups. Typically a methyl group (-CH3) is substituted for oxygen in SiO2, and the result is an overall "loosening" of the lattice, a reduction in film density, and a corresponding reduction in the k value. However, this does not lower k enough in comparison to spin-on solutions containing nanopores.
As shown in Table 3, the issue of technology extendibility and introduction is clouded. This is mainly due to the larger infrastructure for applying CVD films that currently exists is the industry. At this date, the issue being debated is whether to extend CVD processes to 0.13Ã‚Âµm and change to spin-on at the 0.1Ã‚Âµm technology node. As an alternative, spin-on solutions could be implemented at 0.13Ã‚Âµm while developing process and integration schemes for extension down to 0.1Ã‚Âµm and smaller. For the 0.13m generation, both CVD and spin-on materials exist. However, few CVD options exist for the 0.1Ã‚Âµm generation and smaller. On the other hand, well defined solutions exist for spin-on materials.
Table 3. Dielectric Materials Organized by Applications Method and
Proposed Technology Generation.
What are some other process issues with low-k dielectrics
Early integrators of low-k films encountered problems of resist and via poisoning. Via poisoning has been a widespread problem with the fabrication of dual damascene structures. Via poisoning occurs when etched and stripped dielectric sidewalls absorb moisture prior to via filling, leading to metal corrosion and high via resistance. The source of the poisoning may be the dielectric itself, the processes involved or the integration scheme; and, a poisoned resist makes it impossible to complete the dual damascene structure.
The other significant integration challenge, resist poisoning, is caused by the reaction of amine-based byproducts with chemically amplified photoresists. This reaction, neutralization of the generated photoacid, prevents resist dissolution during develop. Resist poisoning can be brought about by plasma sources that convert nitrogen or ammonia gases to atomic nitrogen that quickly react with hydrogen and diffuse into the low-k films. The gas is later released from the film, and it interacts with the photoresist. Both of these issues require significant process work to control the flow of material to eliminate the contamination.
Etch issues have arisen (microtrenching, profile control and resist stripping).However, a dual hardmask integration scheme has shown improvements in those areas. This approach has been the key to successful development of the copper/SiLK dielectric scheme at IBM. The hardmask approach protects the dielectric during CMP, and new support structures have been used to prevent damage during operations such as packaging.
One of the biggest challenge in copper CMP is the balance between under-polish, which leaves residue and leads to shorting, and over-polish, which erodes and dishes features. To increase durability of the low-k film, a capping layer can be used, but a lower-k film such as SiC is preferred rather than silicon nitride that will increase the effective k value. Polishing SiC layers is more difficult because dishing and erosion in densely patterned areas is more likely than in the blanket film areas.
One way of circumventing a low-k material's lack of mechanical strength is to implement it only at the line levels, using SiO2 at via levels. Beyond firming up the structure, this "embedded" approach can reduce moisture absorption, prevent via poisoning, and allow the fab to keep conventional dry etch and cleaning process for the vias. The embedded structure also makes for a more compatible CMP process, while allowing a company to learn from gradual integration of the low-k material. However, it seems few companies will take this approach due to the added complexity of processing and cost associated with maintaining two ILD processes.
The copper cannot be etched as it does not form volatile compounds with other materials.so another method was developed. This process is called Damascene process. Here the process used is an extended version of this method called Dual Damascene process. These are the various points coming under this process:
Used to create multi-level, high density metal interconnections. Because copper does not form a volatile by-product, it is very difficult to etch.
Dual damascene technique overcomes this problem by eliminating metal etch and dielectric gap fill.
May be up to 20% less expensive than traditional interconnect fabrication techniques. Interconnect lines are created by first etching a trench or canal in a planar dielectric and then filling that trench with metal. The metal is then planed back to the surface of the ILD using chemical-mechanical polishing. A series of holes (contact or vias) are then etched and filled. The order of etching may be varied (trench-first or via-first) and is now mostly via first. Problems With Damascene In trench-first, photo-resist pools in the trenches after etching, making it difficult to etch fine via structures. Residual photo-resist may be absorbed by the ILD, contaminating it, and altering its k value. Most low-k films are hydrophilic in character. Surface hard mask must shield the ILD from moisture during the copper CMP process.
It must also block copper diffusion, and act as a CMP stop.
Barrier material must act as an embedded etch stop when used in the middle of an ILD stack. Requires the etch rate to be significantly slower than that of the ILD. Currently silicon nitride is used to perform these multiple roles. LD). Eventually the k-value (6<k<8) will become unacceptable. (It drives up the total k of the I
SiC:h is being investigated a substitute for silicon nitride. SiC:h
Properties of the SiC:h are:
Next generation barrier material.
Has good adhesion characteristics.
Makes an excellent CMP stop.
Forms a good etch stop layer (slow etch rate relative to low-k materials).
Forms a good diffusion and moisture barrier.
Lower k value than silicon nitride.
As a new material, requires more study.
FUTURE OF RC DELAY
Figure 4 shows that if semiconductors continue down the path of decreasing feature sizes, interconnect delay will increase even with the adoption of Cu and low-k dielectrics. Equation 3 showed us that RC delay is inversely proportional to the squares of both line pitch and thickness. This indicates that pitch and thickness cannot continue to be decreased at all levels. A hierarchical wiring approach could minimize delay in the future. In a hierarchical structure, successive wiring levels have increasing width and thickness to enable long runs with low RC delay.
Referring to Equation 1, increasing P and T, each by a factor , causes resistance to fall by 1/2. However, this has no effect on capacitance as shown in Equation 2. In IBMâ„¢s MOS7S logic at the first copper level, the minimum contacted pitch is 0.63m. It is 0.81m at successive levels, and the pitch and thickness of the 5th and 6th levels can be optionally scaled by a factor of 2X. In general, schemes that combine hierarchical wiring (with Cu and low-k) and appropriate circuit design techniques can prevent interconnect delays from overwhelming gate delays. Conventional wiring schemes have avoided hierarchical structures by reducing the pitch and increasing the aspect ratio. However, increasing the aspect ratio much further is not practical, as any benefit will be offset by the increase in line to line or sidewall capacitance (see Equation 2).
In addition to hierarchical wiring, cryogenic cooling could be implemented to decrease RC delay. As shown in Equation 2, capacitance is insensitive to cross-sectional geometry, and the dielectric constant of the materials cannot be less than 1. Therefore, one of the only factors left is the resistance of the line. By cryogenically cooling the lines, even the resistance of aluminum can be significantly reduced. Although this is impractical at this time, this could be implemented in the future.
Optical interconnects are another area in which significant focus has been placed. Most schemes suggest hybrid circuits where optical signals are generated by components that are bonded to the silicon chip instead of integrated into the silicon structure. Potential advantages of optical interconnects include the following:
elimination of resistive loss;
reduced power consumption;
avoidance of frequency-dependent cross talk;
improved electrical noise immunity; and,
wavelength division multiplexing (WDM â€œ one optical connection replaces many wires).
However, for microprocessors, on-chip optical interconnections may only replace the widest and thickest signal wires as optical interconnects are typically larger.
The IntelliGen 2 photochemical dispense system is uniquely positioned to filter and dispense low-k dielectric materials. The IntelliGen 2 photochemical dispense system contains Mykrolis Corporationâ„¢s patented Two-Stage Technology (TST). TST provides both superior dispense performance and elimination of fluid contaminants by allowing independent control of filtration rate and dispense rate (i.e., each rate can be programmed to achieve optimal performance). Unlike conventional filtration and dispense technology, the filter is not downstream of the dispense pump. In a TST system, the filter is between the two stages, and this has the following beneficial effects:
Dispense volume accuracy and repeatability are no longer affected by pressure fluctuations due to filter pressure variability, filter loading and hydraulic capacitance caused by trapped bubbles in the filter. The result is an accurate and repeatable dispense even at extremely low dispense volumes â€œ important factors for both process control and improved Cost of Ownership (COO) of the dielectric process.
Some wafer defects can be rate sensitive (soft gel passage, bubble passage and microbubble formation). These defects can either be eliminated or minimized by low rate filtration.
When starting-up a new system, it is necessary to recirculate the fluid through the system to eliminate entrapped air and bubbles. Studies have shown particle count benefit with recirculation.58 The IntelliGen 2 photochemical dispense system uses closed loop recirculation of the fluid to remove bubbles and particle from the fluid. Once the fluid is conditioned, this clean fluid can then be dispensed onto the wafer. This will minimize fluid consumption and improve COO.
Low hold-up volume to minimize the amount of chemical needed to prime and flush the system at start-up and at shutdown.
Some of these materials use solvents that have low threshold limit values (TLVs) for solvent vapor exposure to ensure operator safety.
The integrated filter on the IntelliGen 2 photochemical dispense systems allows for the fastest filter change with no tools and minimal solvent exposure. Not only does this improve operator safety, but equipment uptime and overall equipment effectiveness (OEE) can be increased as well. Successful evaluations of the IntelliGen 2 photochemical dispense system has been completed on many different low-k dielectric materials (e.g., SiLK, CYCLOTENE (BCB), FLARE, HOSP, FOx, etc) in applications labs at chemical manufacturers. In addition, IntelliGen 2 photochemical dispense systems and other Mykrolis two-stage dispense systems are in use at many chipmaker sites where they have demonstrated the previously mentioned benefits.
In addition to Cu wiring, new, low-k dielectrics are needed to prevent interconnect delay from increasing dramatically. Unfortunately, there is no single low-k material for every application. As previously stated, significant differences in applications and chip architecture may preclude using one such material. However, at this time, the following trends are clear:
For 0.13m processes, many different spin-on low-k dielectrics are being integrated successfully into device structures including HSQ, SiLK, FLARE, FOx, VELOX and BCB.
At and below the 0.1m technology node, porous organic and inorganic materials will take over. The path to extend the chemicals to lower dielectric constants appears clear, but process changes may be needed to accommodate the mechanical and thermal properties of these materials.
CVD processes are clearly at the wall and the viability of extending these processes to k values for the 0.1m node and lower is unclear.
For porous materials, which are the future of dielectric materials, significant process support will be required to overcome the limitations of these materials.
VLSI technology , Sze
Integrated circuits, Botkar
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1. INTRODUCTION 01
2. INTERCONNECTS 03
3. CAPACITANCE 06
4. THE NEED FOR NEW DIELECTRICS 07
5. POROUS MATERIALS 21
6. DEPOSITION METHODS 26
7. DUAL DAMASCENE 30
8. FUTURE OF RC DELAY 32
9. CONCLUSIONS 35
10. REFERENCES 36