The effect of microprocessor pipeline depth on performance is considered. It is found that pipeline depth is a tradeoff between various factors, including the degree of superscalar processing, fraction of pipeline hazards, the fabrication technology of the processor, and the processor workload. The degree of instruction level parallelism decreases the optimal pipeline depth, while the lack of pipeline stalls increases the optimal pipeline depth. As we increase pipeline depth, there is a competition between greater pipeline throughput and pipeline hazards. An expression is derived relating the pipeline depth to these parameters.