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silicon on plastic full report
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The plastic substrates are thinner, lighter, shatterproof, flexible, rollable and foldable, making Silicon-on-Plastic an enabling technology for new applications/products. This paper studies the development of Silicon on Plastic technology. Advances in poly-silicon technology have expanded TFT (THIN FILM TRANSISTORS) technology to high-speed electronics applications such as Smart Cards, RFID tags, portable imaging devices, photo-voltaic devices and solid-state lighting and other integrated circuit functions.

The challenge of Silicon-on-Plastic technology is to overcome the fact that plastic melts at the temperature required to build transistors in conventional TFT processes. Technological innovations have been made to accommodate silicon processing at low temperatures. This paper describes an innovative ultra-low temperature poly-silicon TFT process on plastic substrates , Key technologies includes near room-temperature silicon and oxide deposition steps, laser crystallization and dopant activation. Manufacturing issues related to plastic material compatibility in a TFT process are reviewed. Lamination and de- lamination of plastic wafers to glass carrier wafers for manufacturability is discussed. An active matrix TFT backplane will be fabricated with an OLED (Organic Light Emitting Diode) display to demonstrate this technology.

Currently, amorphous silicon thin film transistors (TFTâ„¢s) on glass are predominantly used in the flat panel display industry for notebook computers, mobile phones, PDAâ„¢s (Personal Digital Assistant), and other handheld devices. Today, flat panels made by amorphous TFT technology are replacing desktop computer CRT (Cathode Ray Tube) monitors at an ever-increasing rate. Amorphous TFT technology applications are limited due to its inherently low electron mobility. Applications that require integration of display drivers such as hand-held camcorder and cell phone displays are using poly-silicon based TFTâ„¢s for cost and space savings. This eliminates the need for costly assembly of conventional silicon chips onto the amorphous TFT display panels. Advances in poly- silicon technology have expanded TFT technology to high-speed electronics applications such as Smart Cards, RFID tags and other integrated circuit functions.
Recently developed ultra low-temperature polysilicon TFT technology can be applaid on both glass and plastic substrates. The plastic substrates are thinner, lighter, shatterproof, flexible, rollable and foldable, making silicon-on-plastic an enabling technology for new applications/products. Some of the possibilities are roll-up/down displays, lightweight, thin wall-mounted TVs, electronic newspapers, and wearable display/computing devices. Moreover, plastic substrates offer the potential of roll-to-roll (R2R) manufacturing which can reduce manufacturing cost substantially compared to conventional plate -to-plate (P2P) methods. Other possibilities include smart cards, RFID tags, and portable imaging devices, photo-voltaic devices and solid- state lighting.
The challenge of silicon-on-plastic technology is to overcome the fact that plastic melts at the temperature required to build transistors in conventional TFT processes. The ultra low-temperature process is compatible with plastic substrates and offers good TFT performance. Technological innovations have been made to accommodate silicon processing at low temperatures.
Low temperature (< 100º C) gate oxide deposition:
A proprietary deposition machine and a compatible process were developed to deposit high quality TFT gate oxides at sub-100º C temperatures. It is a special PECVD (Plasma-Enhanced Chemical Vapor Deposition) system with an added plasma source configuration akin to ECR (Electron Cyclotron Resonance) to generate high-density plasma at low temperature. The process is optimized to provide high-density plasma for silicon dioxide deposition using SiH4 and O2. The gate oxide film at 100 nm thickness has a breakdown voltage of more than 70V, while the gate leakage current density is less than 60 nA/cm2 at 20-V bias.As-deposited gate oxideshows good C-V characterstics . 1. A small amount of hysteresis is observed before annealing takes place. A pre- oxidation plasma treatment step using a mixture of H2 and O2 to grow a very thin oxide at the interface between the deposited silicon and the gate oxide with acceptable interface states was added to the process flow. Sufficiently high-density plasma must be generated in order to grow oxide with any significant thickness. The chuck is cooled to 20º C to keep the plastic temperature below 100º C during the entire pre- oxidation and deposition process. The cleanliness of the Si surface is critical prior to the oxidation process.
The result shown in Figure 1 exhibits the difference between gate oxides with and without pre-oxidation. With pre-oxidation, we obtain an oxide C-V curve very close to the one calculated theoretically.
Poly-silicon laser processing:
A Xe-Cl excimer laser is used to crystallize sputtered silicon on plastic, thereby forming large polysilicon grains for TFTâ„¢s with much higher mobility than its amorphous counterpart. The extremely short laser pulses provide sufficient energy to melt the deposited Si, while the subsequent cooling forms a polycrystalline structure. This crystallization technique is similar to polysilicon formation on glass. The challenge with plastic substrates is to melt the deposited silicon while preserving the structural quality of the underlying base material
C-V curves for gate oxide
1.Excimer Laser Annealing converts amorphous-Si to polysilicon film 30ns Xe-Cl (308nm) pulse produces large grains for high performance TFTâ„¢s 2.SiO2 layer traps heat in silicon layer plastic substrate is not damaged or deformed ,Heat insulation allows full melt of silicon without damaging the plastic substrate . The temperature profiles in the plastic substrate covered with Si and SiO2. The SiO2 layer is sandwiched between the plastic substrate and Si to act as a heat sink preventing the plastic substrate from melting. Fig.3 reflects poly silicon grain size engineering .At first the grain size increases with laser fluence due to the increase of melt depth . Once the full melt threshold(FMT) is fluence on grainsize in the poly silicon film.
reached , all si seeds are melted , the film crystallizes by homogeneous nucleation of super cooledmolten si ,resulting in a uniform fine grain structure . The peak of the FMT is apparent in figure . To maintain reasonable uniformity in grain sizes and operate the laser reproducably , the laser fluence is selected to grow grains slightly above half micron diameter . The same laser system is used to perform dopant activation and annealing after source/ drain ion implantation . again it provides nearly S/D dopant activationwith out damaging the plastic underneath the Si layer. Plastic handling: Lamination and de-lamination processes In order to use standard automated semiconductor manufacturing tools , a lamination/de-lamination process is develped to handle the flexible substrates. The plastic sheets are cut into 6-inch wafer formats and laminated onto carrier wafers made of glass. This allows for processing the full TFT or active-matrix back plane using standard tools with plastic laminated glass wafers. The wafers are delaminated at the completion of the wafer processing. The schematic of process sequence is illustrated Both sides of the plastic wafer are coated with a proprietary hard-coat material that increases resistance to scratches and chemicals.
Additionally, the hard coat helps planarize the plastic surface, which is typically rougher than a standard display-grade glass. The plastic wafers are then processed through a heat- stabilization cycle, referenced to the plastic materialâ„¢s glass transition temperature (Tg). This cycle helps relieve internal stresses and reduces plastic deformation in subsequent processing steps. In addition, the lamination process has to satisfy several stringent requirements. The total flatness of the resulting sandwich needs to be tightly controlled to avoid issues in the photolithographic steps that follow. The laminate material thickness has to be optimized to minimize peak-to-valley variations. The lamination process cannot trap air bubbles between the laminated films. It also needs to withstand wet processing (solvents in particular) and to be clean and dry to meet deposition chamber requirements, such as minimum moisture and solvent out-gassing. The laminated wafer needs to be processed so that the plastic wafers can be delaminated safely and easily from the glass carrier wafers after the TFT manufacturing process is completed. This must be accomplished without inducing structural damage or adversely affecting the electrical properties of the TFT devices. The same TFT process is used for laminating plastic wafers as for glass wafers. This lamination technique enables the full use of automated processing tools. After completing the process and delamination, the plastic wafers retain their original flexibility .
Another important consideration is the maximum temperature tolerated by the laminated wafer during the process. This depends on both the type of plastic and on the type of laminate chosen. At present, polyimide films are used for the plastic substrate, and the process temperature is limited by the stability of the laminate to about 110ºC. The ultra low temperature poly-silicon TFT process used ensures adhesion of the laminate throughout the process and minimizes issues in subsequent lithography layer-to-layer registrations.
Once the full process has been completed and the flexible substrate is detached, it can be post-annealed at a higher temperature, as allowed by the chosen plastic type.Because of the critical requirement on alignment accuracy at lithographic steps, the most important process parameter is dimensional stability during the entire fabrication process. Using a proprietary heat stabilization treatment prior to wafer processing, it is possible to reduce the run-out to meet the requirements of current design rules (~4 µm).
Integration Issues and TFT performance:
In order to make an integrated circuit using TFTâ„¢s, all process modules including the ones mentioned above must be fully integrated. The process sequence shown down the fig re device is shown in the fig .5 presents a simple 4-mask TFT process. The cross-sectional view of a finished TFT . It is a top-gate device structure with source/drain regions self-aligned to the aluminum (Al) gate.
A refractory metal Mo(Molybdynum), is used as first level of metal, but it is known to have a high level of film stress. However, it is also possible to use Al and/or an Al/Mo composite metallization scheme to reduce stress caused by Mo. This is a unique integration issue associated with plastic substrates due to their sensitivity to film stress. This causes too much dimensional instability and run-out problems. Improvement in run- out is obtained using the Al/Mo composite metallization instead of a pure Mo film.
In a display, a storage capacitor is included to mitigate a small amount of off current (or leakage current) from the TFT. One or two additional masks are needed to make the capacitor. Depending on the type of display mate extra processes steps are needed. For example, if a bottom-emitting OLED is used, it is necessary to add a transparent second contact level, often called Via. This requires two additional masks. However, these masks are not needed if a top-emitting OLED device is used. The subsequent deposition of the OLED film and another layer of a cathode material completes the display.
As described earlier, plastic substrate integrity is maintained during laser recrystallization since most laser energy is absorbed in the deposited amorphous film with a relative thick SiO2 layer underneath. However, during source/drain implant activation when Si islands have already been formed, laser damage can occur in the area where the plastic substrate is no longer covered by a blanket silicon layer. To resolve this a Bragger reflector layer was embedded in between the plastic substrate and the Si layer. By using alternating oxide/nitride layers plastic damage is avoided.
Another important integration issue is plastic substrate control during gate oxide deposition. To avoid excessive run-out, cooling is needed for the plastic substrate, however excessive cooling leads to poor oxide quality due to lack of mean free path during SiO2 nucleation .
channel TFT
plastic sheet is de-laminated, low off current is achieved using a 300°C hydrogen plasma anneal process.
All relevant device parameters are summarized in Table
1. The electrical TFT device characteristics on glass substrates are similar to these TFTâ„¢s made on plastic substrates. The ultra low-temperature polysilicon TFT described above has been used to fabricate active matrix backplanes on glass and plastic substrates. The backplanes were then used to make display demos with OLED. To reduce defects, attention is focused on cleanliness and handling of the TFT samples prior to the OLED deposition. Back-planes are shipped to partners for OLED film deposition.
The dynamic properties of plastic substrates such as flexibility,rollability,foldability light weight etc.., made us to have this effective and efficient polysilicon technology i.e..,SILICON ON PLASTIC for manufacturing TFTâ„¢S(Thin Film Transistors). Moreover, plastic substrates offer the potential of roll-to-roll (R2R) manufacturing which can reduce manufacturing cost substantially compared to conventional plate-to-plate (P2P) methods . This advanced technology made us to have high speed electronic applications such as smart cards , RFID tags , portable imaging devices , photo voltaic devices etc..,No doubt , this technology will create new trends in fabrication industry and we hope that the products emerged from this technology will reach everyone at low cost .


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