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smart pixel arrays full report
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Smart pixels, the integration of photodetector arrays and processing electronics on a single semiconductor chip, have been driven by its capability to perform parallel processing of large pixelated images and in real-time reduce a complex image into a manageable stream of signals that can be brought off-chip. In recent years, optical modulators and emitters have been integrated with photodetectors and on-chip electronics. The potential uses for smart pixels are almost as varied as are the designs. They can be used for image processing, data processing, communications, and that special sub-niche of communications, computer networking. While no immediate commercial use for smart pixels has risen to the forefront, smart pixels systems are utilizing technology developed for a wide variety of other commercial applications. As lasers, video displays, optoelectronics and other related technologies continue to progress, it is inevitable that smart pixels will continue to integrate along with these commercially successful technologies.


High speed smart pixel arrays (SPAs) hold great promise as an enabling technology for board-to-board interconnections in digital systems. SPAs may be considered an extension of a class of optoelectronic components that have existed for over a decade, that of optoelectronic integrated circuits (OEICs). The vast majority of development in OEICs has involved the integration of electronic receivers with optical detectors and electronic drivers with optical sources or modulators. In addition, very little of this development has involved more than a single optical channel. But OEICs have underpinned much of the advancement in serial fiber links. SPAs encompass an extension of these optoelectronic components into arrays in which each element of the array has a signal processing capability. Thus, a SPA may be described as an array of optoelectronic circuits for which each circuit possesses the property of signal processing and, at a minimum, optical input or optical output (most SPAs will have both optical input and output).

The name smart pixel is combination of two ideas, "pixel" is an image processing term denoting a small part, or quantized fragment of an image, the word "smart" is coined from standard electronics and reflects the presence of logic circuits. Together they describe a myriad of devices. These smart pixels can be almost entirely optical in nature, perhaps using the non-linear optical properties of a material to manipulate optical data, or they can be mainly electronic, for instance a photoreceiver coupled with some electronic switching.
Smart pixel arrays for board-to-board optical interconnects may be used for either backplane communications or for distributed board-to-board communications, the latter known as 3-D packaging. The former is seen as the more near-term of the two,

Figure 1
employing free-space optical beams connecting SPAs located on the ends of printed circuit boards in place of the current state-of-the-art, multi-level electrical interconnected boards. 3-D systems, on the other hand, are distributed board-to-board optical interconnects, exploiting the third dimension and possibly employing holographic interconnect elements to achieve global connectivity (very difficult with electrical interconnects).
Most work in high speed SPAs has involved the use of either multiple-quantum-well (MQW) modulators or vertical-cavity surface-emitting lasers (VCSELs) as the optical source, and each of these has taken one of two approaches, monolithic and hybrid (e.g., monolithic VCSELs/GaAs and hybrid VCSELs/Si). The hybrid approaches are rapidly gaining popularity since they can take advantage of mainstream silicon microelectronics for the pixel logic circuitry, thereby leveraging the 30 billion dollar silicon semiconductor industry.

Figure 2
The figure shows a very simple depiction of a VCSEL showing the substrate, layers of GaAs and AlAs that form the Bragg planes, the quantum well region where gain occurs, the p and n doped regions that make the p.n. diode junction
In a discussion of light source modulated smart pixels, it is necessary to understand the devices that produce the light. The Vertical Cavity Surface Emitting Laser (VCSEL) is a very important and useful light source.
VCSELS utilize a quantum well structure to confine charges to an active region much like edge emitting lasers. The main difference between VCSELS and other semiconductor lasers is the vertical structure. Most semiconductor lasers are planar and emit out of the edge facet on all sides. This configuration allows more active region than in VCSELS. The vertical lasers are constructed from the same planar epitaxy method as the edge emitting lasers, then etch back is used to produce a cylindrical structure. Because the light spends a relatively small amount of time in the gain region, it is necessary to optimize the cavity. Layers are grown such that they form Bragg planes so that light with the desired wavelength is preferentially propagated. This structure is illustrated in figure. The VCSEL is crucial to smart pixel applications because of the ability of VCSELS to form two dimensional arrays. They are constructed out of material that is convenient for fabrication of photodetectors and in some cases logic, so, devices like VCSELS and FCSELS can be utilized in monolithic smart pixels.
The VCSEL/Si Smart Pixel Arrays

The VCSEL-based SPAs that will be discussed are hybrid components involving GaAs optoelectronic chips and Si electronic chips. Creating a hybrid Si/GaAs structure involves epitaxially growing GaAs on Si or bonding the two together. Although the former is likely to lead to faster SPAs, it has proven to be a low yield process because of the large lattice mismatch that exists between GaAs and Si, leading to unacceptable GaAs defect levels for fabricating laser diodes. One way to combine the GaAs and Si chips is to mount both onto a common base substrate which can support electrical microstrips between the two chips.
The conventional way of doing this is to bond both to the base substrate with their device sides up and then to electrically connect them by wire bonding both chips to the microstrips and their associated bonding pads on the base substrate. For large array sizes, an unrealistic amount of space on the chips and on the base substrate will be devoted to bonding pads, and the length of the electrical connections between the chips will defeat much, if not all, of the advantage of the optical interconnects. Borrowing a technique from the emerging technology of multi-chip module (MCM) fabrication, the chips can be placed device-side down (called flip-chip) and bump bonded to the carrier. Bump bonding has the distinct advantage that chip connections can be made anywhere on the surface of the chip rather than being confined to the chip's periphery as is the case for wire bonding. This most often leads to a shortening of interconnect lengths, thereby enabling higher speed operation. Furthermore, bump bonding can establish all chip connections in parallel, thus reducing production time for large arrays. Flip-chip bonding of the optoelectronic chip to the base substrate leads to an important constraint on this substrate. Since the optical sources now face the substrate, it must be transparent to permit the optical beams to pass through to the outside of the hybrid structure.

Figure 3.
Glass is the material that can be used due to cost considerations, but the superior thermal properties of sapphire make it very appealing from all but the cost viewpoint. A packaged SPA based on the flip-chip bonding of both the VCSEL array and the electronic array (containing the detectors, processing elements and laser drivers) to a transparent base substrate is shown in figure 3. A hole is drilled in the well of a conventional ceramic package to allow passage of both the incoming and outgoing light beams. Note that the transparent substrate provides a convenient base on which to mount both refractive and diffractive optical devices. Although only shown in the path of the outgoing beams, such beam forming and directing devices could be used in the path of the incoming beams also (e.g., to focus the beams onto the detectors).
The VCSEL chip contains an 8x8 array of top-emitting VCSELs with a 250 µm pitch grown on a GaAs substrate. Each VCSEL consists of a single quantum well active region surrounded by distributed Bragg reflectors, and has been ion implanted for current confinement in the active region. The threshold currents of the VCSELs are between 2.5 and 3.0 mA, the operating currents are less than 8 mA at 2 V, and the output powers are approximately 1 mW. 90 µm square bonding pads for attachment of the flip-chip bonds are evenly interspersed amongst the VCSELs, each pad located a distance of 125 µm (center-to-center) from its associated laser element. The silicon (CMOS) chip contains an 8x8 processing element (PE) array, an 8x8 photoreceiver array, an 8x8 VCSEL driver array, and a 9x15 bonding pad array. Details of the three 8x8 arrays are given in the following paragraphs.

Figure 4.
Each PE is a 1-bit wide processor that can operate at 20 MHz and consists of an arithmetic logic unit, a logic circuit which can perform 16 logic functions, a full adder, a 32-bit shift-register, 6 static registers, and some control circuits. Although the PEs are capable of general purpose processing, they were designed with FFT processing in mind. The PEs are electrically connected to their nearest neighbors to facilitate localized processing. Each PE also has 4 Kbits of RAM memory that is located off-chip due to on-chip space restrictions. The chip was fabricated through MOSIS using the 2 µm CMOS process.
Each photoreceiver consists of a p-n junction photodiode, a current mirror amplifier, and two voltage comparators. The first comparator converts the current signal to a voltage signal, while the second comparator is used to boost the voltage to 5 volts when the incident optical signal is modulated higher than 10 MHz. The photoreceiver can respond to an incident optical power of 100 µW at 14 MHz modulation. Each VCSEL driver consists of two logic inverters and a pass gate, and can operate at 20 MHz. The drive current passing through the gate and on to the VCSEL can be varied by adjusting the gate voltage, thereby affording an independent current adjustment for each VCSEL. The circuit was designed so as not to dissipate power in the OFF state.
The transparent substrate that is used is glass, as opposed to sapphire, due to cost considerations and the lack of severe thermal dissipation requirements at array sizes of only 8x8. Sapphire may need to replace glass for large size arrays. The transparent substrate is patterned with the electrical interconnects that provide connectivity between the chips and the package and between the VCSEL and CMOS chips themselves. The thickness of the substrate was selected so as to position the microlenses (lenslet array) at the correct focal length.
The lenslet array is a standard product of Nippon Sheet Glass. Its purpose is to collimate the VCSEL beams prior to their diffraction by the holographic optical interconnect element (HOIE). The center-to-center spacing of the microlenses in the array is 250 µm to match the pitch of the VCSEL array.
The holographic optical interconnect element (HOIE) contains 64 individual phase holograms (one per VCSEL) that diffract the VCSEL beams so as to implement a non-separable perfect shuffle interconnection between two identical SPAs). The HOIE was custom designed as a four-level diffractive optical element using special CAD tools.
Thermosonic flip-chip bonding to mount both the VCSEL chip and the CMOS chip to the glass substrate. The principles of thermosonic flip-chip bonding are the same as those for conventional ultrasonic wire bonding except that all of the bonds must be made simultaneously. This new flip-chip technique was developed in place of the conventional techniques used in multi-chip module (MCM) fabrication because of the different environment that exists in working with optoelectronic chips. For example, solder reflow involves "dirty" processes such as solder deposition and flux during reflow, and it is very difficult to deposit solder on a chip once it has been diced. Also, the aluminum pads usually found on CMOS chips are incompatible with most solder technologies used in MCM fabrication. Conductive epoxy attachment is not feasible since the conductive particles interfere with the optical paths. Finally, thermocompression bonding involves higher temperatures and pressures, which could possibly damage the mechanical stress sensitive VCSEL chip. Thermosonic bonding uses ultrasonic energy to help "soften" the bonding material, thereby achieving bonding at lower temperature and pressure than thermo-compression bonding. For the fabrication of our smart pixel arrays, the VCSEL chips are flip-chip bonded to the base substrates by first plating gold bumps (30 µm diameter by 20 µm high) onto the gold surface contact pads of the VCSEL array. These plated contacts are then accurately positioned relative to the contacts on the substrate. The parts are then joined by a combination of heat, normal force, and ultrasonic energy.
Since the CMOS chips are received already diced, plating the bumps is not feasible. Gold balls are bonded to the aluminum contacts by a conventional wire bonding process, and the wires are subsequently removed. The remainder of the bonding process is the same as for the VCSEL chips.
The glass substrates with their bonded CMOS and VCSEL chips are then mounted in ceramic packages which have had holes drilled in their bottoms in order to provide optical access to and from the photodetectors and VCSELs, respectively, The package is then closed by adding the heat-sink/ground-plate (in contact with the back-side of the VCSEL chip through a thermally conducting grease). After closure, the lenslet arrays are glued to the exposed side of the substrate (opposite side from the bonded chips), and the hologram arrays are glued to the top of the lenslet arrays.
Figure 5
The figure is of one of SPAs as viewed through the hole in the ceramic package. The small square is the 8x8 VCSEL array, and the large rectangle is the CMOS chip (top sides of both chips visible through the glass substrate). Intra-package electrical interconnect traces on the glass are also visible. This picture was taken before the lenslet and hologram arrays were added.
Figure 6
Applications requiring the communication of digital data on the order of a trillion bits per second (terabits/second) will require the high rates achievable with optical channels. There are two applications that are driving current developments in free-space optical interconnection: telecommunication-datacommunication switching networks (e.g., ATM switches) and fine-grained parallel computers. For the former, customer access to multimedia is projected to require the switching of hundreds of thousands of subscriber lines, each running at over 500 Mb/s. This results in throughputs that are three to four orders of magnitude beyond the capacity of existing telecommunication networks, and one to two orders of magnitude beyond the projections for current electrical interconnect technology. In the case of fine-grained parallel computers, the need for tight coupling between tens of thousands of processing elements, each running near Gb/s data rates, also exceeds the projected capabilities of electrical interconnects.
An example of a fine-grained parallel system is illustrated in figure 6. This real-time graphics engine was designed to handle 1280x1024 pixels at 10 samples/pixel with 48 bits per sample for operation at 30 frames/second. Although such a performance sounds impressive, it falls more than two orders of magnitude short of rendering the number of polygons per second needed for true realism in most virtual reality applications. The desirable bandwidth would accommodate 1800x1100 pixels (HDTV) at 16 samples/pixel with 256 bits/sample for operation at 72 frames/second. This requires a board-to-board throughput of 580 Gbits/second, well in excess of the Semiconductor Industry Association (SIA) roadmap projection of a 100 Gbit/second throughput for a 256-bit wide bus by the year 2010. Many of these datacommunication switching network and parallel computer applications involve multiple boards with very high interboard throughput rates. As noted, the system above could use 580 Gbits/second. Over a bus 256 bits wide, this would require each line rate to be in excess of 2 Gbits/second. If the 128x128 SIMD array were to be replaced by a 128x128 smart pixel array (same functionality but optical I/O associated with each pixel), the line rate would have to be only 35.4 Mbits/second, a very reasonable rate.

Figure 7

The backplane of the figure 6 would be replaced by what is called a 3-D system as illustrated in figure 7 in which the board-to-board interconnects are light beams that fill much of the area vertical to the boards. The 3-D system that is assembled for FFT processing consists of just two smart pixel arrays, but the optical interconnects are bi-directional so that data are passed back and forth between the SPAs. The system's 128 PEs run at a 10 MHz clock, yielding an interconnect throughput of 160 MBytes/sec. Control of the 3-D computer is performed by a host computer through the host interface unit. Software and data are down-loaded to the interface at run time, and results are retrieved after completion.

Figure 8.
The 3-D computer is designed to operate in the Single-Instruction stream, Multiple-Data stream (SIMD) mode. Separate data are loaded into the local memory of each processor. A single instruction bus, driven by a sequencer in the host interface, simultaneously controls all the processors. Although the system is capable of general purpose processing, it was designed for FFT processing. With this in mind, the holograms were designed to implement the non-separable perfect shuffle. Details of the optics for the system are shown in figure 9. The laser beam from each VCSEL is first collimated by a microlens and then directed to a designated photodetector on the opposing SPA by a Fourier-transform type computer generated hologram and a Fourier transform lens. The system is symmetrical around the Fourier transform lens.

Figure 9.
Although microlenses and holograms could be used with the photodetectors to help focus the light, but not use them in this demonstration. Instead, it was fabricated relatively large photodetectors (175 µm square). Tools were developed for optical system design and optical crosstalk estimation. The crosstalk estimation for the FFT processor is only 30db.
A unique optomechanical structure is fabricated featuring a portable and modular design concept. The custom optomechanical system allows and aids various optical tests and precision alignment of the 3-D system, and it allows for the replacement of malfunctioning SPAs. It was designed to decouple the alignment procedures of all motion parameters (x,y,z,[alpha],[beta],[phi]) as much as possible.

Figure 10.
There are three system modules that are integrated and aligned by the optomechanics: the Fourier transform lens and the two SPAs. The lens is held tightly by the ring and lens housing. The lens housing is screwed into the inner cylinder at an appropriate "z" position so that the focal length of the lens falls on to the detector plane. In a similar fashion, the outer cylinder is installed. This assembly forms the lens module with a defined "z" position for location of the two SPA substrates. This lens module is then integrated with the two SPAs through connection plates which are glued to the ceramic packages of the SPAs and through the lens module connectors as shown in the figure. The modules are glued following an active alignment procedure that will not be described here. This optomechanics has a volume of less than 12 cm3
The major goals will be to achieve more compact packaging and to scale the SPAs to larger array dimensions. The former not only leads to smaller components, but shortens electrical connections within the SPA, thereby leading to higher potential speeds. It also supports the second goal since scaling can lead to excessively long electrical connections within the SPA for the current packaging methodology.
More compact VCSEL/Si smart pixel arrays
Future development will enable tighter coupling between the VCSEL and the Si chips than is possible with the transparent substrate scheme currently used. If the VCSEL chip is made to emit light in the opposite direction (i.e., in the direction of its substrate), it becomes possible to flip-chip this chip directly onto the Si chip, thereby minimizing the length of the electrical connections between the processing elements and the VCSELs (the two device surfaces are now facing one another). This is necessary if large-dimension high-speed (GHz) SPAs are to be realized. Since high-speed operation also necessitates a higher performance photodetector array than is possible in CMOS, it will be necessary to bond this photodetector array as well as the VCSEL array to the CMOS chip. The figure 11 illustrates such a smart pixel array. There are at least three possible ways to realize backside-emitting VCSEL arrays. First, the VCSELs can be made to emit in the wavelength region in which GaAs is transparent. This is the case for wavelengths longer than approximately 940 nanometers (nm) (most VCSELs are now being fabricated for wavelengths in the region of 830 to 840 nm). Second, the common wavelength VCSELs (830-840 nm) may be able to be grown on a substrate that is transparent at those wavelengths. Third, following the flip-chip bonding process, it may be possible to either remove or sufficiently thin the GaAs substrate to prevent significant absorption. These are all fertile areas for research and development.

Figure 11.
Once substrate-emission VCSEL arrays are available, another problem remains to be solved before these arrays can be flip-chip bonded to silicon chips, that of heat removal from such a hybrid structure. Since light must exit from the backside of the VCSEL chip, a heatsink must either be transparent (e.g., diamond film) or must be attached to the silicon substrate and the VCSEL heat drawn to the silicon through the bonds. Until diamond films with close to 100% transparency are available, the latter approach is more acceptable. Initial estimates are that an 8x8 array of bump bonds will be capable of removing several watts of power from a VCSEL chip. At present, we are experiencing power dissipation levels for 8x8 VCSEL arrays in excess of 2 watts, but this is expected to decrease by at least an order of magnitude over the next few years. However, the 2 watt figure is probably a realistic goal for SPAs since increased efficiencies will likely be accompanied by increased array dimensions (e.g., 32x32 arrays). Another design problem must address whether heat sinks can adequately remove the combined heat of the VCSEL and silicon chips, including the VCSEL drivers. Our silicon-based VCSEL drivers are running at 10 MHz and dissipating about 15 milliwatts each.
The flip-chip bonding of two separate chips onto the CMOS chip still leads to the separation of devices within each pixel. The ultimate goal is to co-locate the VCSEL, photodetector, and logic circuitry for each pixel. This can be accomplished by integrating each VCSEL with a photodetector and providing a bonding pad for each. An array of these integrated VCSELs and photodetectors is then flip-chip bonded on to the CMOS chip as shown below such that the circuitry associated with each VCSEL/detector pair is located directly beneath the pair on the CMOS chip.

Figure 12.
The optical input, optical output, and pixel circuitry are in a single location, thereby minimizing the electrical connections between the three. Future smart pixel array development should consider one other aspect of integration, that of integrating the lenslet arrays, either with the glass substrate (original scheme) or with the GaAs substrate (future scheme). At present, commercial lenslet arrays are used which are poorly matched to the VCSEL beam profiles and which are difficult to align. Smaller alignment errors will allow smaller photodetectors, resulting in faster systems.
Scaling VCSEL/Si smart pixel arrays
Understanding the manufacturing cost minimization issues involved in scaling to larger array sizes is important in meeting market place demands for SPAs. Since smaller VCSEL arrays are more reliable and less expensive, it may be more cost effective to partition large dimensional SPAs into smaller units. A scaling model needs to be realized in order to characterize packaging effects on the assembly yield. This model should provide quantitative guidelines to transfer one system design to another. This can then provide the system designer the option of building N x N arrays from 4 N/2 x N/2 arrays, 16 N/4 x N/4 arrays, etc. It is critical to guide the designs of these novel SPA-based systems so as to enhance reliability and reduce manufacturing cost. The scaling model should predict assembly yields for different options.
A major bottleneck in today's computing systems is the mostly serial communications used between the processing elements and long term memory (e.g., CDs and Zips). This bottleneck is particularly noticeable when fetching (or writing in the case of writable media) high resolution images. If large 2-D data fields, such as images, could be stored as a 2-D pattern of digits on a storage media, a 2-D smart pixel array could fetch these fields in parallel blocks rather than one or a few bits at a time. Data retrieval rates could improve by orders of magnitude, depending on the size of the smart pixel arrays and the ability to develop techniques for parallel error detection and correction.
Thus Smart pixels, the integration of photodetector arrays and processing electronics on a single semiconductor chip, have been driven by its capability to perform parallel processing of large pixelated images and in real-time reduce a complex image into a manageable stream of signals that can be brought off-chip.

1. ËœProgress and prospects of long wavelength VCSELsâ„¢
Connie J. Chang-Hasnain ,University of California,
IEEE Optical Communication ,February 2003.



I extend my sincere gratitude towards Prof. P. Sukumaran Head of Department for giving us his invaluable knowledge and wonderful technical guidance
I express my thanks to Mr. Muhammed Kutty our group tutor and also to our staff advisor Ms. Biji Paul for their kind co-operation and guidance for preparing and presenting this seminars.
I also thank all the other faculty members of AEI department and my friends for their help and support.

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