This seminars presents a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this seminars is to describe the design and quantify its performance impact. Trace-driven simulations show that software managed address translation is just as efficient as hardware managed translation. Moreover, to support such features as shared memory, direct memory access, fine-grained protection can be defined completely in software, and it will add more flexibility than in hardware- defined mechanisms. For the design of memory management system we have returned to first principles and discovered a set of hardware structures that provide support for address space protection, shared memory, large sparse address spaces, and fine grained protection at the cache level. We show that address translation can be managed in software efficiently, achieving similar performance compared to TLB-based systems with very low overhead designs.