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vlsi projects
Post: #1

a) FPGA implementation
b) Implementation and prototyping on 8051 core architecture on FPGA
c) Implementation of 12C controller on FPGA
d) A VLSI Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
e) An FPGA-Based Architecture for Real Time Image Feature Extraction
f) A Low-Power Multiplier with the Spurious Power Suppression Technique
g) A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
h) Block-Based Multiperiod Dynamic Memory Design For Low Data Retention Power
i) Controllable Arbitrary Integer frequency divider based on VHDL
j) Compliant Digital Base band Transmitter on a Digital Signal Processor
k) Design and implementation of spectral estimation algorithm on FPGA
l) Design and analysis of low density parity check encoder for fixed and mobile wireless access systems
m) Design analysis of 1-Gigabit Ethernet media access controller(gemac) core for full-duplex operation
n) Design and turbo convolution code decoder for 3GPP wireless mobile communication systems
o) Design and implementation of orthogonal frequency division multiple access modem on FPGA
p) Development of keyboard controller for single board computer based on FPGA
q) Design and discrete cosine transform processor on FPGA for video compression applications
r) Design and development of traffic light controller on FPGA
s) Design and implementation of CAN Controller on FPGA
t) Design Exploration of A Spurious Power Suppression Technique (SPST) And itâ„¢s Applications
u) Design Of Reconfigurable Coprocessor for Communication Systems
v) Digital system control for Three Degree of Freedom Mechanical Arm with FPGA
w) Design and implementation of Digital Camera System on Chip
x) Development of 8051 microcontroller synthesizable model and implementation on FPGA
y) Development of intellectual property for local interconnect network for automobile sensor interface applications
z) Design and implementation of finite impulse response filter in FPGA using VHDL
aa) Implementation of A Multi-Channel UART Controller Based On FIFO Technique and FPGA
bb) Implementation of IEEE 802.11 a WLAN base band Processor
cc) On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics
dd) Optimized Software Implementation of a Full-Rate IEEE 802.11a
ee) The CSI Multimedia Architecture
ff) VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
gg) VHDL implementation of direct sequence spread spectrum modulator for personal secure communication in battle filed
hh) A lossless data compression and decompression algorithm and its hardware architecture
ii) A Verilog impimentation of UART Design with Bist Capability
jj) A Robust UART Architecture based on Recursive Running Sum Filter for Better Noise Performance
kk) An area-efficient Universal Cryptography Processor for smart cards
ll) An FPGA based general purpose data acquisition controller
mm) A PicoBiaze-Based Embedded system for monitoring applications
nn) A VHDL Model of IEEE1451.2 Smart Sensor: Characterization and application
oo) Design and prototyping of portable media player asic on FPGA
pp) Development of Huffman encoder for MPEG-2 video encoding applications
qq) Design of real time clock on FPGA for portable hand held applications
rr) Development of FPGA based PCI bus arbiter multiprocessor Environment
ss) Design and implementation of adaptive differential pulse code modulation encoder and decoder ip for communication applications
tt) Development of video display processor on FPGA
uu) FPGA Implementation of USB Transceiver Macro cell Interface With Usb2.0 Specifications
vv) FPGA Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
ww) FPGA based Power Efficient Channelizer for Software defined Radio
xx) FPGA based implementation communication modulation
yy) Fuzzy based PID Controller using VHDL/VERILOG for Transportation Application
zz) Improvement of the orthogonal Code Convolution Capabilities using
Post: #2
a) Processor and the Reconfigurable Logic on an FPGA
b) Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers
c) A Novel Multiplexer-Based Low-Power Full Adder
d) Registers for Phase Difference Based Logic
e) Logical Reversibility of Computation
f) Reconfigurable Architecture for Network Flow Analysis
g) The Reconfigurable Instruction Cell Array
h) Cost-Efficient SHA Hardware Accelerators
i) Fast Elliptic Curve Cryptography on FPGA
j) System Architecture and Implementation of MIMO Sphere Decoders on FPGA
k) Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
l) A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
m) A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
n) Blind Separation of Superimposed Shifted Images Using Parameterized Joint Diagonalization
o) Efficient Communication Between the Embedded
p) A coding framework for low power address and data busses
q) Spread Spectrum Signaling for Speech Watermarking
r) A Lightweight Encryption Method Suitable For Copyright Protection
s) A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture
t) Concurrent Error Detection in Reed“SolomonEncoders and Decoders
u) VLSI Implementation of Multiplier-Free Low Power Baseband Filter for CDMA Systems
Post: #3
can u send me full report on adjustable bidirectional moc current mirror?? pls it s urgent..
Post: #4
plz send me the ppt of Reconfigurable Architecture for Network Flow Analysis

plz my mail id sreeraj1989[at]

need urgent
Post: #5
the proj topic given is "low power low area wallace tree multiplier".
i have no idea about how to begin.
my knowledge in vlsi is just the basic and mostly theory based, have no idea abt cells, pla pal etc.
please advice how to go about with starting the project.Huh
Post: #6
visit this thread for more details on the wallace tree multipliers:

For implementing the project, the most easiest method will be to design the system using VHDL or Verilog coding and then implement it on an FPGA board. There are very goog tutorials available in the net about the FPGA and VHDL
Post: #7
please send me report and ppt of "verilog implementation of uart design with Bist capability.

my mail id is " shwethadv[at] "
Post: #8
can u send me full report on "A Verilog impimentation of UART Design with Bist Capability"

urgent plz send me yar
Post: #9
please send me the project report and code for vlsi design and analysis of low power 6t sram cell and a high speed 32 bit signed/unsigned pipelined multiplier.
Post: #10
to get information about the topic" vlsi projects"refer the link bellow
Post: #11
[attachment=15750][attachment=15749] please send me the verilog code for this mini projects
Post: #12
hi my name is savan patel..
my topic is gps based mobile tracking for uml
send the my id:-savan_patel14593[at]
Post: #13
to get information about the topic vlsi projects full report ppt and related topic refer the link bellow

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